• Microelectronics
  • Vol. 53, Issue 3, 500 (2023)
HAN Weimin1, LIU Jiao2, WANG Lei2, HONG Ming3, ZHU Kunfeng2, and ZHANG Guangsheng2
Author Affiliations
  • 1[in Chinese]
  • 2[in Chinese]
  • 3[in Chinese]
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    DOI: 10.13911/j.cnki.1004-3365.220324 Cite this Article
    HAN Weimin, LIU Jiao, WANG Lei, HONG Ming, ZHU Kunfeng, ZHANG Guangsheng. A Macro Model for LDMOS with Annular Gate[J]. Microelectronics, 2023, 53(3): 500 Copy Citation Text show less
    References

    [2] BEZHENOVA V, MICHALOWSKA-FORSYTH A. Modeling of annular gate MOS transistor [C] // 2018 18th European Conference on Radiation and its Effects on Components and Systems (RADECS). Goteborg, Sweden. 2018: 44-47.

    [3] STROHBEHN K, MARTIN M N. SPICE macro models for annular MOSFETs [C] // 2004 IEEE Aerospace Conference Proceedings. Big Sky, MT, USA. 2004: 2370-2377.

    [4] LOPEZ P, BLANCO-FILGUERIA B, HAUER J. Modeling and experimental results of short channel annular MOS transistors [C] // 2011 20th European Conference on Circuit Theory and Design (ECCTD). Linkping, Sweden. 2011: 685-688.

    [5] XIA K, INDANA H, GOGINENI U. Compact modeling of LDMOS working in the third quadrant [C] // Proceedings of the IEEE 2014 Custom Integrated Circuits Conference. San Jose, CA, USA. 2014: 821-824.

    [6] IIZUKA T, NAVARRO D, MIURA-MATTAUSCH M, et al. Predictive compact modeling of abnormal LDMOS characteristics due to overlap-length modification [C] // 2020 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD). Kobe, Japan. 2020: 157-160.

    [9] DEY S, SONNET A, VARGHESE D, et al Generalized sub-circuit model to enable accurate CHC aging simulation and spatial defect profiling in LDMOS [C] // 2022 34th IEEE International Symposium on Power Semiconductor Devices and ICs (ISPSD). Vancouver, BC, Canada. 2022: 241-244.

    [10] SASSE G T, SUBRAMANIAN V, RADIC L. Aging models for n- and p-type LDMOS covering low medium and high VGS operation [C] // 2021 IEEE International Reliability Physics Symposium (IRPS). Monterey, CA, USA. 2021: 751-756.

    [11] MAHAJAN B K, CHEN Y P, ALAM M A, et al. A critical examination of the TCAD modeling of hot carrier degradation for LDMOS transistors [C] // 2022 IEEE International Reliability Physics Symposium (IRPS). Dallas, TX, USA. 2022: 10A.2-1-10A.2-7.

    HAN Weimin, LIU Jiao, WANG Lei, HONG Ming, ZHU Kunfeng, ZHANG Guangsheng. A Macro Model for LDMOS with Annular Gate[J]. Microelectronics, 2023, 53(3): 500
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