A capacitor-less Low dropout regulator(LDO) with a low quiescent current and high transient response was designed through a SMIC 0.18 μm BCD process. The error amplifier adopts trans-conductance enhancement to achieve higher loop gain and unit gain bandwidth under low static current conditions. Owing to the use of high gain error amplifiers, the transient response can be enhanced by appropriately reducing the power transistor size. The secondary pole of the loop was increased using active feedback, without introducing additional static current.Simultaneously, when the output voltage of the LDO changed, the dynamic current of the power transistor gate could be increased, achieving a high transient response. In addition, through active feedback, a feedback resistor connected in parallel with a small capacitor was adopted to improve the loop stability. The software Cadence Spectre was used to simulate and verify the LDO circuit. The results show that the static current of LDO is 10 μA. When the load current is 1 mA, the maximum phase margin reaches 70.9°. When the LDO load current is switched from 1 to 100 mA with a switching time of 500 ns, the undershoot voltage is 134.7 mV, and the recovery time of the undershoot voltage is 1 μs. When the LDO load current is switched from 100 to 1 mA with a switching time of 500ns, the overshoot voltage is 155.5 mV, and the recovery time of the overshoot voltage is 430 ns.