Low-pressure plasma technology is very mature in the semiconductor industry and is used in material etching in binary optics. The technology has been divided into capacitively coupled plasma (CCP) and inductively coupled plasma (ICP). The purpose of the technology in binary optics is to create uniform plasma in a bigger space, which could present a better etching effect. The removal rate of the low-pressure plasma is not high enough to fabricate a large aspherical mirror. However, atmospheric pressure plasma has a remarkable removal rate on several optical materials, which is very suitable for fabrication of a large mirror. The disadvantage of atmospheric pressure plasma is that it is too difficult to maintain uniformity in a larger space. To avoid this disadvantage, a three co-axial quarts tubes ICP plasma torch is used to create high temperature and stable plasma in a certain space. Using the given fabrication procedure, it is possible to fabricate a high-accuracy aspherical mirror used in outer space.

Applying atmospheric pressure plasma for fabricating a large optical mirror was developed in the 2000s; its micro-fabricating mechanism is very similar to low-pressure plasma etching.

CCP has been studied by many researchers and has already been applied in many industrial fields, especially in the field of fabricating optical components under vacuum and atmospheric conditions. Wang^[1] fabricated K9 optical glass, diameter 24 mm, and fused silicon, diameter 25 mm, in vacuum. Wang^[2] polished a SiC wafer, surface roughness Ra 0.46 nm, after polishing. A paper on fabrication of optical surfaces on silica glass plates using plasma chemical vaporization machining (CVM)^[3–5], with a 2.0-mm internal diameter “pipe” electrode, producing surfaces of 0.77 nm Ra (0.97 nm Rq) roughness, was published in 1998. The most outstanding work was reported^[6–8] from IOM company in Germany. This technique has been developed to obtain a high removal rate especially on silicon-based materials. Removal depths of some 10 mm are readily achieved. However, the low volume removal rate is the most noteworthy disadvantage.

ICP is a mature method in spectrum analysis, but it is a brand-new technology in optical fabrication. The RAPT company^[9] in the United States is cooperating with Cranfield University^[10–13] on developing reactive atom plasma technology. Helios 1200 is their magnum opus. The production is proposed as a candidate figuring process that combines nanometer level accuracy with high material removal rates. The rapid figuring capability of the RAPT process has already been proven on medium-sized optical surfaces made of silicon-based materials.

The ICP technology has been developed in Changchun Institute of Optics, Fine Mechanics and Physics (CIOMP) as plasma chemical etching technology (PCET). PCET is used to fabricate kinds of optical materials such as reaction bonded (RB)–SiC, sintered SiC (S-SiC), fused silica, and Si. The removal characteristics of the experiments in CIOMP has been published^[14]. Our work is focused on the surface-roughness-modulating characteristics of a mirror fabricated by PCET.

A schematic picture of the front part of the plasma source is given in Fig. 1(a) and a working picture of the plasma source is given in Fig. 1(b).

The ICP torch of PCET is driven by the 2000 W RF generator, frequency 27.12 MHz; the plasma source is matched by the matching network of the RF generator. The cooling gas is Ar, the plasma gas is also Ar, and the reactive gas is CF4 and O2 (oxygen is used in fabricating the SiC material). The energy from the RF generator is coupled into the plasma gas through a three-turn copper tube coil. Because the plasma gas is not a good conductor, the tesla coil should be needed to assist in lighting up the ICP torch. The working procedure is described as the follows. The torch is a three co-axial quartz tube structure, the cooling gas flows between the outer tube and intermediate tube at 15 slm, the plasma gas flows between the intermediate tube and inner tube at 300 sccm, and the reactive gas flows through the inner tube at 0–150 sccm. The Ar environment is set up in the ICP torch at first, and the discharge is introduced by the tesla coil. Then the discharge in Ar environment will light up the plasma gas under the excitation of RF power. The reactive gas is injected into the inner tube, and the gas will be excited by the lit-up Ar plasma into fluorine radicals and oxygen radicals. The radicals will react with the Si-based materials easily. The reaction products are volatile, which offers a method of removing the workpiece material. The final reaction process is described with chemical equationsSi+CF4+O2→SiF4↑+CO2↑,(1)SiC+4O→SiO2+CO2↑,(2)SiO2+4F→SiF4↑+O2↑.(3)All experiments were carried out on RB–SiC, fused silica, and Si samples. Table 1 shows the experimental parameters.

As far as the experimental results are concerned, the surface roughness will increase after fabrication with PCET. The situation is much more obvious, especially on the RB–SiC wafer. The dual-phase micro-structure (Si phase and SiC phase) of the RB–SiC material is the main cause of the rough surface. The Si phase of the wafer will be removed first, because the Si–Si bond energy is weaker than the Si–C bond energy in the SiC phase. The final fabrication result is that the Si phase is always removed first, which causes micro-indentations on the RB–SiC wafer. Removing the Si phase first will eventually increase the surface roughness, irrespective of the fabrication process. The micro-structure results are observed directly in Fig. 2, which were screened by an Olympus LEXT 450. A larger quantity of Si phase in the wafer corresponds to an increased surface roughness. As far as the results are concerned, it is a principle problem which is difficult to solve by improving PCET. Ameliorating the RB–SiC producing procedure is the only final solution. The aforementioned situation is better for S-SiC. Compared with results, the fabrication experiment is carried out on the S-SiC wafer with PCET under the same working condition. Figures 3(a) and 3(b) show the S-SiC wafer micro-structure before fabrication by the PCET. Figure 3(a) a 200× magnified image; the scale bar is 50 μm. Figure 3(b) shows a 2000× magnified image; the scale bar is 10 μm. Figures 3(c) and 3(d) show the S-SiC wafer micro-structure after fabrication by the PCET. Figure 3(c) shows a 200× magnified image; the scale bar is 50 μm. Figure 3(d) shows a 2000× magnified image; the scale bar is 10 μm. The dual-phase characteristic is not clearly observed in Figs. 3(a) and 3(b). However, in Figs. 3(c) and 3(d), the micro-structure is changed slightly; the obvious porous structure emerges on the fabricated wafer surface, which is strongly related to the isotropic characteristic of PCET. If the wafer’s initial surface roughness is small, the fabricated surface is good. In contrast, when the wafer initial surface roughness is larger, the fabricated surface will be the same as the results in Figs. 3(c) and 3(d). According to the results in Figs. 3(c) and 3(d), the desirable removal rate will be obtained, if PCET is combined with computer controlled optical surfacing (CCOS) or magnetortheological finishing (MRF), which is used to fabricate the mirror after PCET. Compared with the surface roughness result before PCET, the wafer surface roughness after PCET is almost the same as beforehand. This conclusion is also verified by the quantitative measurement results.

As for fused silica and silicon, they are all mono-phase materials in theory; the wafer surface roughness fabricated with PCET will be very small. However, in the process of the fabrication, some unknown materials deposit on the wafer, which has a severe influence on the final wafer surface roughness. However, the deposition on the wafer can be removed through a traditional polishing method such as CCOS or MRF. The white material in Fig. 4(b) is the deposition after fabrication of PCET.

Based on the experiments and analyses of several materials, and combining CCOS or MRF with PCET, we found that using CCOS or MRF to polish a wafer after PCET is a good method to obtain a smaller surface roughness. This is a new technique combination; the parameters should be optimized to obtain the best fabrication result.

To obtain quantitative results, surface roughness testing experiments were performed on three different wafers fabricated with PCET. Zygo NewView 7200 and Mitutoyo Surface SJ410 were used to test three wafers. The former equipment is used to test a smooth surface; the latter equipment is used to test a rough surface which cannot be tested with an optical method. The working pictures of the testing equipment are displayed in Figs. 5(a) and 5(b). The testing results are shown in Figs. 6–9.

As far as the fused silica wafer is concerned, there is too much deposition on the wafer fabricated with PCET to be tested by Zygo NewView 7200; consequently, Mitutoyo Surface SJ410 is a better option; the testing result is displayed in Fig. 6(c). To compare with the result in Fig. 6(c), anther fused silica wafer that was not fabricated with PCET was tested under the same condition; the test result is shown in Fig. 6(b). Figure 7(b) is the same situation. After fabrication with PCET, the RB–SiC wafer surface is too rough to be tested by Zygo NewView 7200 because of its dual-phase micro structure. Figures 8(b) and 8(c) indicate the S-SiC wafer surface roughness test results before and after PCET. Combining the Olympus LEXT 450 test result in Figs. 3(c) and 3(d), the trend of increased surface roughness of mono-phase S-SiC is not obvious. Figure 9 shows the unpolished Si wafer surface roughness results before and after PCET.

Figure 10 is wafers surface roughness modulation in the process of PCET.

Analyzing the testing results, the wafer surface roughness increases after fabrication with PCET. The fused silica wafer roughness increases 5 times. If the fused silica wafer is fabricated with PCET first, then polished with CCOS or MRF after the PCET procedure, this will result in a better surface quality (i.e., reduced surface roughness). In the process of CCOS or MRF, the deposition on the wafer will be removed quickly. The RB–SiC wafer surface roughness increases rapidly, almost 40 times. On the contrary, the S-SiC wafer roughness does not change obviously, only 1.07 times. Compared with an RB–SiC wafer, the situation of the Si wafer is much better; the surface roughness only increased to twice that which it had been previously. The surface roughness measurement results of four wafers prove the validity of the aforementioned hypothesis. The dual-phase material surface roughness increases rapidly after fabrication with PCET. However, the main reason why the mono-phase material surface roughness increases is that the reaction products deposit on the wafer.

The Letter is focused on a new inductively coupled PCET operating at atmospheric pressure. PCET is a successful method in terms of fabricating fused silica, RB–SiC, S-SiC, and a Si optical mirror. It has much potential compared with CCOS and IBF. The surface roughness experiments are carried out on four different material wafers. After PCET experiments, it is found that the wafer surface roughness all increased to different extents. As far as mono-phase materials such as fused silica and Si are concerned, the main reason for the roughness increase is the fluoride deposition on the wafer surface during the fabrication process. The fluoride deposition can be completely removed by use of CCOS or MRF. The S-SiC is a mono-phase material; the micro-hole structure emerges on the S-SiC wafer surface after fabrication with PCET, which slightly increases the wafer surface roughness. As for RB–SiC, it is a dual-phase material; typically, the Si-phase material removal rate is higher than the SiC-phase in the plasma circumstance, which leads to the emergence of indentations on the wafer surface. Consequently, the RB–SiC wafer surface roughness clearly increases after fabrication with PCET. Overall, the reason for the wafer surface roughness increase is deduced through examining the wafer micro-structure. Combining the advantages of the PCET high removal rate and CCOS or MRF readily yielding an excellent mirror surface roughness, the PCET has great promise in terms of fabricating a large aspherical mirror.