• Microelectronics
  • Vol. 51, Issue 5, 647 (2021)
WU Yanhui, CHEN Peng, LI Jie, ZHANG Xiaoyong, LAN Shu, LIU Yongguang, and XU Hua
Author Affiliations
  • [in Chinese]
  • show less
    DOI: 10.13911/j.cnki.1004-3365.200407 Cite this Article
    WU Yanhui, CHEN Peng, LI Jie, ZHANG Xiaoyong, LAN Shu, LIU Yongguang, XU Hua. A Monolithic Low Phase Noise and Wideband Frequency Synthesizer[J]. Microelectronics, 2021, 51(5): 647 Copy Citation Text show less
    References

    [1] BARB G, OTESTEANU M. 4G/5G: a comparative study and overview on what to expect from 5G [C]//IEEE TSP. Milan, Italy. 2020: 37-40.

    [2] ROESSLER A. Impact of spectrum sharing on 4G and 5G standards a review of how coexistance and spectrum sharing is shaping 3GPP standards [C]//IEEE EMCSI. Washington D C, USA. 2017: 704-707.

    [3] KAWAI S, AOYAMA H, ITO R, et al. An 802.11ax 4×4 spectrum-efficient WLAN AP transceiver SoC supporting 1024QAM with frequency-dependent IQ calibration and integrated interference analyzer [C]//IEEE ISSCC. San Francisco, CA, USA. 2018: 442-444.

    [4] MENON A V, GUNJEGAI A, AISHWARYA A, et al. Combined amplitude and phase noise effects in QAM direct conversion receivers [C]//ICMOCE. Bhubaneswar, India. 2015: 346-348.

    [5] YU S A, BAEYENS Y, WEINER J, et al. A single-chip 125-MHz to 32-GHz signal source in 0.18-μm SiGe BiCMOS [J]. IEEE J Sol Sta Circ, 2011, 40(3): 598-614.

    [6] OSMANY S A, HERZEL F, SCHEYTT J C. An integrated 0.6-4.6 GHz, 5-7 GHz, 10-14 GHz, and 20-28 GHz frequency synthesizer for software-defined radio applications [J]. IEEE J Sol Sta Circ, 2010, 45(9): 1657-1668.

    [7] RONG S, YIN J, LUONG H C. A 0.05- to 10-GHz, 19- to 22-GHz, and 38- to 44-GHz frequency synthesizer for software-defined radios in 0.13-μm CMOS process [J]. IEEE Trans Circ Syst-II: Expr Bri, 2016, 63(1): 109-113.

    [8] HANGMANN C, WULLNER I, HEDAYAT C, et al. Modeling and characterization of CP-PLL phase noise in presence of dead zone [C]//IEEE NEWCAS. Trois-Rivieres, Canada. 2014: 349-352.

    [10] SU P E, PAMARTI S. Mismatch shaping techniques to linearize charge pump errors in fractional-N PLLs [J]. IEEE Trans Circ Syst I: Regu Pap, 2010, 57(6): 1221-1230.

    [11] COLLINS T E, MANAN V, LONG S I. Design analysis and circuit enhancements for high-speed bipolar flip-flops [J]. IEEE J Sol Sta Circ, 2005, 40(5): 1166-1174.

    [12] GU Q J, GAO Z. A CMOS high speed multi-modulus divider with retiming for jitter suppression [J]. IEEE Microw Wirel Compon Lett, 2013, 23(10): 554-556.

    [13] HOSSEINI K, KENNEDY M P. Minimizing spurious tones in digital delta sigma modulators [M]. New York: Springer, 2011: 19-21.

    WU Yanhui, CHEN Peng, LI Jie, ZHANG Xiaoyong, LAN Shu, LIU Yongguang, XU Hua. A Monolithic Low Phase Noise and Wideband Frequency Synthesizer[J]. Microelectronics, 2021, 51(5): 647
    Download Citation