Author Affiliations
State Key Laboratory of Advanced Optical Communication Systems and Networks, Department of Electronic Engineering, Shanghai Jiao Tong University, Shanghai 200240, Chinashow less
Fig. 1. Data synchronization and buffering in optical networks.
Fig. 2. Photonics-assisted microwave beam forming and steering in phased array radar systems.
Fig. 3. Microwave photonic delay-line filter with a finite impulse response. PD, photodetector; VOA, variable optical attenuator; MUX, multiplexer; DEMUX, demultiplexer.
Fig. 4. Typical system configuration of optical coherence tomography.
Fig. 5. Four-channel pulse interleaver using WDM-TDM implemented on a silicon chip
[27].
Fig. 6. Three types of cascaded ring resonator delay lines: (a) SCISSOR; (b) CROW in transmission mode; (c) CROW in reflection mode.
Fig. 7. Four types of integrated BGs with periodic modulation of (a) waveguide height, (b) waveguide width, (c) slab width, and (d) cladding.
Fig. 8. (a) Standard grating waveguide and its delay spectrum. (b) Cascaded complementary apodized gratings
[74].
Fig. 9. BG delay line based on a 60-nm-thick silicon waveguide
[35].
Fig. 10. ODLs based on (a) chirped BG
[73] and (b) linearly chirped contra-directional couplers with uniform BG
[80].
Fig. 11. ODL based on (a) line-defect PhCW and (b) coupled-cavity PhCW.
Fig. 12. Schematics of the switchable ODLs in (a) parallel and (b) serial configurations.
Fig. 13. 1×N optical switches based on (a) cascaded 1×2 switch elements and (b) optical phased array.
Fig. 14. (a) Architecture of the continuously tunable ODL structure; (b) mask layout of the ODL chip
[110].
Fig. 15. Recirculating loop delay line. (a) Integrated buffer; (b) gate matrix switch
[113].
Fig. 16. Recirculating loop delay line in a parallel switchable configuration.
Fig. 17. AWG-based wavelength-selective true-time-delay line. (a) Working principle illustration; (b) AWG layout.
Fig. 18. Implementation of an ODL based on frequency-to-time mapping.
ODLs | Delay Tuning Range (ps) | Resolution (ps) | Bandwidth (nm) | Delay Loss (dB/ps) | Power Efficiency (mW/ps) | Footprint () |
---|
SCISSORs[47] | 345 | Small | | 0.06 | 0.07 | 0.125 | CROWs[37] | 800 | Small | 0.02 | 0.01 | 0.15 | 5 | Grating[80] | 96 | Small | 0.8 | 0.001 | 11 | 0.015 | PhCWs[91] | 54 | Small | | 0.17 | 11 | 0.06 | 4 bit SiN RTTDL[107] | 12350 | 850 | Large | 1.9 × 10−4 | 0.02 | 3825 | Continuously tunable RTTDL[110] | 1280 | Small | 0.48 | 0.01 | 0.05 | 28.62 | Wavelength-selective delay line[117] | 600 | 40 | 0.4 | 0.011 | – | 640 | Recirculating loop delay line[113] | 1100 | – | 2 | 0.002 | – | 60 | MEMS[121] | 94 | Small | | 0.24 | – | |
|
Table 1. Performance Comparison of Several Typical Integrated ODLs