• Microelectronics
  • Vol. 52, Issue 5, 764 (2022)
CHENG Han, YE Yidie, PAN Chunbiao, and XI Zhenghui
Author Affiliations
  • [in Chinese]
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    DOI: 10.13911/j.cnki.1004-3365.220347v Cite this Article
    CHENG Han, YE Yidie, PAN Chunbiao, XI Zhenghui. An Adaptive Dead Time Control Circuit for GaN Gate Drive[J]. Microelectronics, 2022, 52(5): 764 Copy Citation Text show less
    References

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    [3] LIN Y K, LAI Y S. Dead-time elimination method and current polarity detection circuit for three-phase PWM-controlled inverter [C]// IEEE ECCE. San Jose, CA, USA. 2009: 83-90.

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    [5] HUANG X, LI Q, LIU Z, et al. Analytical loss model of high voltage GaN HEMT in cascode configuration [J]. IEEE Trans Power Elec, 2014, 29(5): 2208-2219.

    [6] CONG L, XUE J, LEE H. A 100 V reconfigurable synchronous gate driver with comparator-based dynamic dead-time control for high-voltage high-frequency DC-DC converters[C]// IEEE APEC. Charlotte, NC, USA. 2015: 2007-2010.

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    [8] SONG M K, CHEN L, SANKMAN J, et al. A 20 V 8.4 W 20 MHz four-phase GaN DC-DC converter with fully on-chip dual-SR bootstrapped GaN FET driver achieving 4 ns constant propagation delay and 1 ns switching rise time [C]// IEEE Int Sol Sta Circ Conf. San Francisco, CA, USA. 2015: 1-3.

    [10] GREZAUD R, AYEL F, ROUGER N, et al. A gate driver with integrated deadtime controller[J]. IEEE Trans Power Elec, 2016, 31(12): 8409-8421.

    [12] XUE J, NGO K D T, LEE H. A 99%-efficiency 1-MHz 1.6-kW zero-voltage-switching boost converter using normally-off GaN power transistors and adaptive dead-time controlled gate drivers [C]// IEEE Int Conf Elec Dev Sol Sta Circ. Hong Kong, China. 2013: 1-2.

    [15] HAN D, SARLIOGLU B.Deadtime effect on GaN-based synchronous boost converter and analytical model for optimal deadtime selection [J]. IEEE Trans Power Elec, 2015, 31(1): 601-612.

    CHENG Han, YE Yidie, PAN Chunbiao, XI Zhenghui. An Adaptive Dead Time Control Circuit for GaN Gate Drive[J]. Microelectronics, 2022, 52(5): 764
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