• Microelectronics
  • Vol. 52, Issue 2, 211 (2022)
YUAN Yidan1, LIN Guowei1, MA Juncheng1, and WU Kejun2
Author Affiliations
  • 1[in Chinese]
  • 2[in Chinese]
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    DOI: 10.13911/j.cnki.1004-3365.zjea002 Cite this Article
    YUAN Yidan, LIN Guowei, MA Juncheng, WU Kejun. A Switch Sequence Optimization Technology for Current Steering DAC[J]. Microelectronics, 2022, 52(2): 211 Copy Citation Text show less
    References

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    [2] GUO T, TANG K, ZHENG Y J, A 1 GHz configurable chirp modulation direct digital frequency synthesizer in 65 nm CMOS [C]// IEEE ISCAS. Daegu, Korea. 2021: 1-4.

    [3] JUAND A, SHU W, CHANG J S. A calibration-free/ DEM-free 8-bit 2.4-GS/s single-core digital-to-analog converter with a distributed biasing scheme [J]. IEEE Trans VLSI Syst, 2018, 26(11): 2299-2309.

    [4] STOOPS D J, KUO J, HURST P J, et al. Digital background calibration of a split current-steering DAC [J]. IEEE Trans Circ & Syst I: Regu Pap, 2019, 66(8): 2854-2864.

    [5] LAI L Q, LI X Q, FU Y S, et al. Demystifying and mitigating code-dependent switching distortions in current-steering DACs [J]. IEEE Trans Circ & Syst I: Regu Pap, 2019, 66(1): 68-81.

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    [8] SHEN M H, HUANG P C. A low cost calibrated DAC for high-resolution video display system[J]IEEE Trans VLSI Syst, 2012, 20(9): 1743-1747.

    [9] LIU M L, ZHU Z M, YANG Y T. A high-SFDR 14-bit 500 MS/s current-steering D/A converter in 018 μm CMOS [J]IEEE Trans VLSI Syst, 2015, 23(12): 3148-3152.

    [10] WU K J, LI J, WANG X Z, et al. Switching sequence optimization for gradient errors compensation in the current-steering DAC design [J]. Microelec J, 2020, 95: 104662.

    [12] CHI J H, CHU S H, TSAI T H. A 18-V 12-bit 250-MS/s 25-mW self-calibrated DAC [C]// Proceed ESSCIRC. Seville, Spain. 2010: 222-225.

    YUAN Yidan, LIN Guowei, MA Juncheng, WU Kejun. A Switch Sequence Optimization Technology for Current Steering DAC[J]. Microelectronics, 2022, 52(2): 211
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