• Microelectronics
  • Vol. 52, Issue 4, 550 (2022)
WANG Wei, LIU Bowen, CHIO U-Fat, ZHANG Dingdong, ZHANG Shan, and XIONG Deyu
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  • [in Chinese]
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    DOI: 10.13911/j.cnki.1004-3365.210333 Cite this Article
    WANG Wei, LIU Bowen, CHIO U-Fat, ZHANG Dingdong, ZHANG Shan, XIONG Deyu. A Capacitor Mismatch Detection and Digital Calibration Technique for SAR ADC[J]. Microelectronics, 2022, 52(4): 550 Copy Citation Text show less
    References

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    [2] DING M, HARPE P, LIU Y, et al. A 46 μW 13 b 6.4 MS/s SAR ADC with background mismatch and offset calibration [J]. IEEE J Sol Sta Circ, 2017, 52(2): 423-432.

    [3] MCNEILL J A, CHAN K Y, COLN M C W, et al. All-digital background calibration of a successive approximation ADC using the “split ADC” architecture [J]. IEEE Trans Circ Syst I: Regu Pap, 2011, 58(10): 2355-2365.

    [4] LAN Z, DONG L, JING X, et al. A 12-bit 100 MS/s SAR ADC with digital error correction and high-speed LMS-based background calibration [C]// IEEE ISCAS. Daegu, Korea. 2021: 1-5.

    [5] LIU W, HUANG P, CHIU Y. A 12-bit 45-MS/s 3-mW redundant successive-approximation-register analog-to- digital converter with digital calibration [J]. IEEE J Sol Sta Circ, 2011, 46(11): 2661-2672.

    [6] WANG G, KACANI F, CHIU Y. IRD digital background calibration of SAR ADC with coarse reference ADC acceleration [J]. IEEE Trans Circ Syst II: Expr Bri, 2014, 61(1): 11-15.

    [7] WU J, WU A, DU Y. Dithering-based calibration of capacitor mismatch in SAR ADCs [J]. Elec Lett, 2016, 52(19): 1598-1600.

    [8] SUN L, DAI Q, LEE C, et al. Analysis on capacitor mismatch and parasitic capacitors effect of improved segmented-capacitor array in SAR ADC [C]// IITA. Nanchang, China. 2009: 280-283.

    WANG Wei, LIU Bowen, CHIO U-Fat, ZHANG Dingdong, ZHANG Shan, XIONG Deyu. A Capacitor Mismatch Detection and Digital Calibration Technique for SAR ADC[J]. Microelectronics, 2022, 52(4): 550
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