• Microelectronics
  • Vol. 52, Issue 6, 1090 (2022)
MA Junxiang1, LIANG Huaguo1, LI Danqing1, YI Maoxiang1..., LU Yingchun1 and JIANG Cuiyun2|Show fewer author(s)
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    DOI: 10.13911/j.cnki.1004-3365.210500 Cite this Article
    MA Junxiang, LIANG Huaguo, LI Danqing, YI Maoxiang, LU Yingchun, JIANG Cuiyun. A Low-Overhead On-Chip Aging Measurement Scheme for Bypass Reconfiguration RO[J]. Microelectronics, 2022, 52(6): 1090 Copy Citation Text show less
    References

    [1] DING D L, ZHANG Y J, WANG P J, et al. Design a delay amplified digital aging sensor circuit in 65 nm CMOS [C]// 13th IEEE ICSICT. Hangzhou, China. 2016: 1449-1451.

    [2] YU L, REN J, LU X, et al. NBTI and HCI aging prediction and reliability screening during production test [J]. IEEE Trans Comput Aid Des, 2020, 39(10): 3000-3011.

    [3] SADEGHI-KOHAN S, KAMAL M, NAVABI Z. Self-adjusting monitor for measuring aging rate and advancement [J]. IEEE Trans Emerg Topics Comput, 2020, 8(3): 627-641.

    [4] BARANOWSKI R, FIROUZI F, KIAMEHR S, et al. On-line prediction of NBTI-induced aging rates [C]// Proceed DATE. Grenoble, France. 2015: 589-592.

    [5] LI X, QIN J, BERNSTEIN J B. Compact modeling of MOSFET wear-out mechanisms for circuit-reliability simulation [J]. IEEE Trans Dev Mater Reliab, 2008, 8(1): 98-121.

    [6] LI Y J, KIM Y M, MINTARNO E, et al. Overcoming early-life failure and aging for robust systems [J]. IEEE Des Test Comput, 2009, 26(6): 28-39.

    [7] JAFARI A, RAJI M, GHAVAMI B. Impacts of process variations and aging on lifetime reliability of flip-flops: a comparative analysis [J]. IEEE Trans Dev Mater Reliab, 2019, 19(3): 551-562.

    [8] SADEGHI-KOHAN S, KAMAL M, NAVABI Z. Self-adjusting monitor for measuring aging rate and advancement [J]. IEEE Trans Emerg Topics Comput, 2020, 8(3): 627-641.

    [9] SAI G, HALAK B, ZWOLINSKI M. Multi-path aging sensor for cost-efficient delay fault prediction [J]. IEEE Trans Cirsyst II: Expr Brie, 2018, 65(4): 491-495.

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    [11] KIM T, PERSAUD R, KIM C H. Silicon odometer: an on-chip reliability monitor for measuring frequency degradation of digital circuits [J]. IEEE J Sol Sta Circ, 2008, 43(4): 874-880.

    [12] WANG X, TEHRANIPOOR M, GEORGE S, et al. Design and analysis of a delay sensor applicable to process/ environmental variations and aging measurements [J]. IEEE Trans VLSI Syst, 2012, 20(8): 1405-1418.

    [13] LIANG H, FANG X, YI M X , et al. A novel BIST scheme for circuit aging measurement of aerospace chips [J]. Chinese J Aeronaut, 2018, 31(7):1594-1601.

    [14] MENBARI A, JAHANIRAD H. A concurrent BIST architecture for combinational logic circuits [C]// 10th ICCKE. Guangzhou, China. 2020: 262-267.

    MA Junxiang, LIANG Huaguo, LI Danqing, YI Maoxiang, LU Yingchun, JIANG Cuiyun. A Low-Overhead On-Chip Aging Measurement Scheme for Bypass Reconfiguration RO[J]. Microelectronics, 2022, 52(6): 1090
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