[2] CHEN Z J, MIYAHARA M, MATSUZAWA A. A 2nd order fully-passive noise-shaping SAR ADC with embedded passive gain ［C］// IEEE A-SSCC. Toyama, Japan. 2016: 309-312.

[3] LIN Y Z, TSAI C H, TSOU S C, et al. A 24-mW 25-MHz BW 300-MS/s passive noise shaping SAR ADC with noise quantizer technique in 14-nm CMOS ［C］// IEEE Symp VLSI Circ. Kyoto, Japan. 2017: 234-235.

[4] LIN Y Z, LIN C Y, TSOU S C, et al. A 40 MHz-BW 320 MS/s passive noise-shaping SAR ADC with passive signal-residue summation in 14 nm FinFET ［C］// IEEE ISSCC. San Francisco, CA, USA. 2019: 330-331.

[5] LIU J X, WANG X, GAO Z J, et al. A 40 kHz-BW 90 dB-SNDR noise-shaping SAR with 4× passive gain and 2nd-order mismatch error shaping ［C］// IEEE ISSCC. San Francisco, CA, USA. 2020: 158-159.

[6] LI S L, QIAO B, GANDARA M, et al. A 13-ENOB 2nd-order noise-shaping SAR ADC realizing optimized NTF zeros using an error-feedback structure ［C］// IEEE ISSCC. San Francisco, CA, USA. 2018: 234-235.

[7] ZHUANG H Y, GUO W J, LIU J X, et al. A second-order noise-shaping SAR ADC with passive integrator and tri-level voting ［J］. IEEE J Sol Sta Circ, 2019, 54(6): 1636-1647.

[8] LIU J X, LI D Q, ZHONG Y, et al. A 250 kHz-BW 93 dB-SNDR 4th-order noise-shaping SAR using capacitor stacking and dynamic buffering ［C］// IEEE ISSCC. San Francisco, CA, USA. 2021: 370-371.

[10] FREDENBURG J, FLYNN M. A 90 MS/s 11 MHz bandwidth 62 dB SNDR noise-shaping SARADC ［C］// IEEE ISSCC. San Francisco, CA, USA. 2012: 468-469.