• Acta Physica Sinica
  • Vol. 69, Issue 17, 177102-1 (2020)
Meng Zhang, Ruo-He Yao*, Yu-Rong Liu, and Kui-Wei Geng
Author Affiliations
  • School of Electronic and Information Engineering, South China University of Technology, Guangzhou 510641, China
  • show less
    DOI: 10.7498/aps.69.20200497 Cite this Article
    Meng Zhang, Ruo-He Yao, Yu-Rong Liu, Kui-Wei Geng. Shot noise model of the short channel metal-oxide-semiconductor field-effect transistor[J]. Acta Physica Sinica, 2020, 69(17): 177102-1 Copy Citation Text show less
    Structure diagram of the NMOSFET device.
    Fig. 1. Structure diagram of the NMOSFET device.
    Schematic diagram of the transistor with a fictitious dc source in the channel.
    Fig. 2. Schematic diagram of the transistor with a fictitious dc source in the channel.
    Full-shot noise and thermal noise vs. gate-source bias voltage (Leff = 40 nm).
    Fig. 3. Full-shot noise and thermal noise vs. gate-source bias voltage (Leff = 40 nm).
    Fano factor of shot noise vs. gate-source bias voltage (Leff = 40 nm).
    Fig. 4. Fano factor of shot noise vs. gate-source bias voltage (Leff = 40 nm).
    Full-shot noise and thermal noise vs. gate-source bias voltage (Leff = 20 nm).
    Fig. 5. Full-shot noise and thermal noise vs. gate-source bias voltage (Leff = 20 nm).
    Fano factor of shot noise vs. gate-source bias voltage (Leff = 20 nm).
    Fig. 6. Fano factor of shot noise vs. gate-source bias voltage (Leff = 20 nm).
    Full-shot noise and thermal noise vs. gate-source bias voltage (Leff = 10 nm).
    Fig. 7. Full-shot noise and thermal noise vs. gate-source bias voltage (Leff = 10 nm).
    Fano factor of shot noise vs. gate-source bias voltage (Leff = 10 nm).
    Fig. 8. Fano factor of shot noise vs. gate-source bias voltage (Leff = 10 nm).
    Meng Zhang, Ruo-He Yao, Yu-Rong Liu, Kui-Wei Geng. Shot noise model of the short channel metal-oxide-semiconductor field-effect transistor[J]. Acta Physica Sinica, 2020, 69(17): 177102-1
    Download Citation