[13] W L Chang, C Meng, G W Huang. SBD layout optimization with effect of N-well to p-substrate pn junctions in 0.18 μm CMOS process(2016).
[13] W L Chang, C Meng, G W Huang. SBD layout optimization with effect of N-well to p-substrate pn junctions in 0.18 μm CMOS process(2016).
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