• Electronics Optics & Control
  • Vol. 29, Issue 11, 82 (2022)
TANG Zixiang1, LYU Fangxu2、3, SHI Jianjun1, ZHANG Jinwang1, WANG Zheng1, and LI Peng1
Author Affiliations
  • 1[in Chinese]
  • 2[in Chinese]
  • 3[in Chinese]
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    DOI: 10.3969/j.issn.1671-637x.2022.11.014 Cite this Article
    TANG Zixiang, LYU Fangxu, SHI Jianjun, ZHANG Jinwang, WANG Zheng, LI Peng. Design of Low-Power-Consumption 112 Gibit/s Duo-binary PAM4 SerDes Transmitter for High Channel Attenuation[J]. Electronics Optics & Control, 2022, 29(11): 82 Copy Citation Text show less
    References

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    [5] CELIK F,AKKAYA A,TAJALLI A,et al.A 32 Gb/s PAM-4 SST transmitter with four-tap FFE using high-impedance driver in 28 nm FDSOI[J].IEEE Transactions on Very Large Scale Integration (VLSI)Systems, 2021,29(6):1132-1140.

    [6] KIM J,KUNDU S,BALANKUTTY A, et al.8.1 A 224 Gb/s DAC-based PAM-4 transmitter with 8-Tap FFE in 10 nm CMOS[C]//IEEE International Solid-State Circuits Conference(ISSCC).San Francisco:IEEE, 2021:126-128.

    [7] KIM J,BALANKUTTY A,DOKANIA R K,et al.A 112 Gb/s PAM-4 56 Gb/s NRZ reconfigurable transmitter with three-tap FFE in 10 nm FinFET[J].IEEE Journal of Solid-State Circuits,2019,54(1):29-42.

    [8] SABER M G,GUTIERREZ-CASTREJON R,XING Z,et al.Demonstration of 108 Gb/s duo-binary PAM-8 transmission and the probabilistic modeling of DB-PAM-M BER[J].IEEE Photonics Journal,2021,13(1):1-14.

    [9] PENG P J,CHEN Y T,LAI S T.et al.6.7 A 112 Gb/s PAM-4 voltage-mode transmitter with 4-tap two-step FFE and automatic phase alignment techniques in 40 nm CMOS[C]//IEEE International Solid-State Circuits Conference(ISSCC).San Francisco:IEEE,2019:124-126.

    [10] MENOLFI C,BRAENDLI M,FRANCESE P A,et al.A 112 Gb/s 2.6 pJ/b 8-Tap FFE PAM-4 SST TX in 14 nm CMOS[C]//IEEE International Solid-State Circuits Conference(ISSCC).San Francisco:IEEE,2018:104-106.

    [11] GROEN E,BOECKER C,HOSSAIN M,et al.6.3 A 10-to-112 Gb/s DSP-DAC-based transmitter with 1.2 Vppd output swing in 7 nm FinFET[C]//IEEE International Solid-State Circuits Conference(ISSCC).San Francisco:IEEE,2020: 120-122.

    [12] TAN K H,CHIANG P C,WANG Y,et al.A 112-Gb/s PAM4 transmitter in 16 nm FinFET[C]//IEEE Symposium on VLSI Circuits.Honolulu:IEEE,2018:45-46.

    [13] SUHR L F,OLMOS J J V,MAO B,et al.112-Gbit/s × 4-lane duobinary-4-PAM for 400GBase[C]//Proceedings of European Conference on Optical Communication (ECOC).Cannes:IEEE,2014:1-3.

    [16] SABER MD G,GUTIRREZ-CASTREJN R,ALAM MD S, et al.100 Gb/s/λ duo-binary PAM-4 transmission using 25G components achieving 50 km reach[J].IEEE Photonics Technology Letters, 2020, 32(3):138-141.

    [17] LEE J,CHIANG P,PENG P,et al.Design of 56 Gb/s NRZ and PAM4 SerDes transceivers in CMOS technologies[J].IEEE Journal of Solid-State Circuits, 2015, 50(9):2061-2073.

    TANG Zixiang, LYU Fangxu, SHI Jianjun, ZHANG Jinwang, WANG Zheng, LI Peng. Design of Low-Power-Consumption 112 Gibit/s Duo-binary PAM4 SerDes Transmitter for High Channel Attenuation[J]. Electronics Optics & Control, 2022, 29(11): 82
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