• Electronics Optics & Control
  • Vol. 29, Issue 11, 82 (2022)
TANG Zixiang1, LYU Fangxu2、3, SHI Jianjun1, ZHANG Jinwang1, WANG Zheng1, and LI Peng1
Author Affiliations
  • 1[in Chinese]
  • 2[in Chinese]
  • 3[in Chinese]
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    DOI: 10.3969/j.issn.1671-637x.2022.11.014 Cite this Article
    TANG Zixiang, LYU Fangxu, SHI Jianjun, ZHANG Jinwang, WANG Zheng, LI Peng. Design of Low-Power-Consumption 112 Gibit/s Duo-binary PAM4 SerDes Transmitter for High Channel Attenuation[J]. Electronics Optics & Control, 2022, 29(11): 82 Copy Citation Text show less

    Abstract

    In order to solve the problem of high bit-error-rate of serial transceiver under strong channel attenuation,a low-power 112 Gibit/s SerDes transmitter is designed by using Duo-binary PAM4 coding technology.By adopting Duo-binary PAM4 coding technology,the problem of excessive attenuation of high-speed PAM4 (Pulse Amplitude Modulation-4) signal is solved.The system power consumption of the transmitter is reduced by using CMOS 1/4 speed architecture for 4∶1 MUX.The linearity of Duo-binary PAM4 transmitter is improved by using impedance calibration circuit.The transmitter is designed by CMOS 28 nm process and powered by 0.9 V voltage.The simulation results show that the transmitter can operate at 112 Gibit/s under the strong channel attenuation of 20.9 dB,with the power consumption of 1.9 pJ/bit and the linearity of 88.3%.
    TANG Zixiang, LYU Fangxu, SHI Jianjun, ZHANG Jinwang, WANG Zheng, LI Peng. Design of Low-Power-Consumption 112 Gibit/s Duo-binary PAM4 SerDes Transmitter for High Channel Attenuation[J]. Electronics Optics & Control, 2022, 29(11): 82
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