A five order symmetry chaotic circuit including memoristor was designed by adopting the method which memoristor replace the piecewise-linear resistance. Based on the four order chaotic circuit proposed by Matsumoto, Chua and Kobayashi (MCK), the model of five order memoristor circuit was built. Conventional dynamics analysis method was used to analyze the equilibrium point set, stability and Lyapunov exponent. Conventional components were used to build simulation model of five order memoristor chaotic circuit and carry out circuit simulation experiments. Theoretical analysis and simulation experimental results show that five order memoristor chaotic circuit designed has rich chaotic behavior, which widen the design and application of memoristor chaos circuit.