• Microelectronics
  • Vol. 51, Issue 6, 838 (2021)
LI Xiangchao
Author Affiliations
  • [in Chinese]
  • show less
    DOI: 10.13911/j.cnki.1004-3365.210050 Cite this Article
    LI Xiangchao. A Fractional Phase-Locked Loop with Low Spurious[J]. Microelectronics, 2021, 51(6): 838 Copy Citation Text show less
    References

    [1] SHU K L, SANCHEZ-SINENCIO E. CMOS PLL synthesizers: analysis and design [M]. Boston: Springer, 2007: 201-209.

    [3] MANAS K H, TARUN K B. A constant loop bandwidth in delta sigma fractional-N PLL frequency synthesizer with phase noise cancellation [J]. Integration, 2019, 65: 175-188.

    [5] ZHOU B, LI Y, ZHAO F Y. Noise and spur comparison of delta-sigma modulators in fractional-N PLLs [J]. J Elec Test, 2019, 35(2): 917-923.

    [6] CHEN Y, PRAAMSMA L, IVANISEVIC N, et al. A 40 GHz PLL with -925 dBc/Hz in-band phase noise and 104 fs-RMS-jitter [C] // IEEE RFIC. Honolulu, HI, USA. 2017: 31-32.

    CLP Journals

    [1] TENG Hailin, MENG Xu, WANG Xiaolei. A High-Performance Fractional-N Cascaded PLL Circuit[J]. Microelectronics, 2022, 52(6): 967