[1] Y J ZHANG, J FAN. An intrinsic circuit model for multiple vias in an irregular plate pair through rigorous electromagnetic analysis. IEEE Transactions on Microwave Theory and Techniques, 58, 2251-2265(2010).
[2] J FAN, X N YE, J KIM et al. Signal integrity design for high-speed digital circuits: progress and directions. IEEE Transactions on Electromagnetic Compatibility, 52, 392-400(2010).
[3] B ARCHAMBEAULT, C BRENCH, S CONNOR. Review of printed-circuit-board level EMI/EMC issues and tools. IEEE Transactions on Electromagnetic Compatibility, 52, 455-461(2010).
[4] T L WU, F BUESINK, F CANAVERO. Overview of signal integrity and EMC design technologies on PCB: fundamentals and latest progress. IEEE Transactions on Electromagnetic Compatibility, 55, 624-638(2013).
[5] T L WU, H H CHUANG, T K WANG. Overview of power integrity solutions on package and PCB: decoupling and EBG isolation. IEEE Transactions on Electromagnetic Compatibility, 52, 346-356(2010).
[6] E P LI, X C WEI, A C CANGELLARIS et al. Progress review of electromagnetic compatibility analysis technologies for packages, printed circuit boards, and novel interconnects. IEEE Transactions on Electromagnetic Compatibility, 52, 248-265(2010).
[7] S JIN, B C CHEN, X FANG et al. Improved “root-omega” method for transmission-line-based material property extraction for multilayer PCBs. IEEE Transactions on Electromagnetic Compatibility, 59, 1356-1367(2017).
[8] L HUA, B C CHEN, S JIN et al. Characterization of PCB dielectric properties using two striplines on the same board, 809-814(2014).
[9] S JIN, X FANG, B C CHEN et al. Validating the transmission-line based material property extraction procedure including surface roughness for multilayer PCBs using simulations, 472-477(2016).
[10] K S CHOW, J ZHANG et al. ASIC package design optimization for 10 Gbps and above backplane serdes links, 199-204(2012).
[11] J ZHANG, W YAO et al. ASIC package to board BGA discontinuity characterization in >10Gbps SerDes links, 569-574(2013).
[12] W YAO, J ZHANG et al. Design of package BGA pin-out for >25Gb/s high speed SerDes considering PCB via crosstalk, 111-116(2015).
[13] S JIN, J ZHANG, J FAN. Optimization of the transition from connector to PCB board, 192-196(2013).
[14] Q ZHU, S VENKATARAMAN, C F YE et al. Package design optimization for intel SoC xeon-D. IEEE Transactions on Components, 8, 531-537(2018).
[15] J ZHANG, W YAO et al. ASIC package to board BGA discontinuity characterization in >10Gbps SerDes links, 569-574(2013).
[16] 16向伟玮, 张继帆, 董东, 等. BGA在微系统宽带射频互连中的应用[J].电子工艺技术, 2016, 37(2): 71-73,93. doi: 10.14176/j.issn.1001-3474.2016.02.003XIANGW W, ZHANGJ F, DONGD, et al. Application of BGA interconnection in wide-band RF microsystem[J]. Electronics Process Technology, 2016, 37(2):71-73,93. (in Chinese). doi: 10.14176/j.issn.1001-3474.2016.02.003
[17] 17刘巍巍, 谭承, 梁栋, 等. 基于BGA技术的毫米波垂直互连设计[C]. 2017年全国微波毫米波会议论文集(中册). 杭州, 2017: 626-629.LIUW W, TANCH, LIANGD, et al. Design on millimeter wave vertical connection using the technology of BGA[C]. 2017 National Microwave and millimeter wave conference, Collection of papers (Volume II). Hangzhou, 2017: 626-629. (in Chinese)
[18] 18周骏, 窦文斌, 沈亚, 等. 应用SIP技术的宽带板间垂直互连结构[J]. 固体电子学研究与进展, 2012, 32(1): 36-39. doi: 10.3969/j.issn.1000-3819.2012.01.008ZHOUJ, DOUW B, SHENY, et al. Broadband vertical transition between substrates in application of SIP technology[J]. Research & Progress of SSE, 2012, 32(1): 36-39. (in Chinese). doi: 10.3969/j.issn.1000-3819.2012.01.008
[19] G KIM, A C W LU, F WEI et al. 3D strip meander delay line structure for multilayer LTCC-based SiP applications, 2081-2085(2008).
[20] F J SCHMUCKLE, A JENTZSCH, W HEINRICH et al. LTCC as MCM substrate: design of strip-line structures and flip-chip interconnects. IEEE MTT-S International Microwave Symposium Digest IEEE MTT-S International Microwave Symposium, 3, 1903-1906(2001).
[21] 21姜兆国, 陈娜, 张路洋. 基于BGA的射频传输性能研究[J]. 电子技术与软件工程, 2018(8): 107-108.JIANGZH G, CHENN, ZHANGL Y. Research on radio frequency transmission performance based on BGA[J]. Electronic Technology & Software Engineering, 2018(8): 107-108. (in Chinese)
[22] S JIN, D Z LIU, B C CHEN et al. Analytical equivalent circuit modeling for BGA in high-speed package. IEEE Transactions on Electromagnetic Compatibility, 60, 68-76(2018).
[23] 23邓国庆, 徐正, 刘向宏, 等. 球栅阵列垂直互联传输性能分析与基板叠层设计[J]. 科学技术与工程, 2021(31): 13381-13388. doi: 10.3969/j.issn.1671-1815.2021.31.024DENGG Q, XUZH, LIUX H, et al. Transmission performance analysis of ball grid array vertical interconnection and stacked substrate design[J]. Science Technology and Engineering, 2021(31): 13381-13388. (in Chinese). doi: 10.3969/j.issn.1671-1815.2021.31.024
[24] Q LU, Y K LIU, Z QIAO et al. A study of a low-loss and ultra-wide band transmission structure through BGA based on HTCC technology, 144-147(2020).