This article proposes a 16-stage on-chip analog accumulation circuit architecture to realize time delay integration(TDI). The accumulation unit is based on charge amplifiers. The temporal noise on the analog signal path of the circuit structure is analyzed to enhance the noise performance, and furthermore the model of thermal noise suitable for the TDI process is given. The analysis revealed that the total thermal noise is composed of charge transfer noise and direct sampled noise, according to different stages of accumulators. The relations of each noise component versus circuit gain and corresponding method to suppress it are given. Finally, a 16×256 test chip is taped out under the 0.5 μm CIS process, and test results indicate the improvement of 11.22 dB in SNR at the 16 TDI stages.