Fig. 1. Excess noise factor of APD FPA and GNDCD with different bias
Fig. 2. Comparison of this article and DRS in NEPh
Fig. 3. I-V curves of NMOS at 77 K and 300 K. The size of the NMOS is W/L=20 μm/0.55 μm
Fig. 4. ROIC overall block diagram
Fig. 5. TDC sequence chart
Fig. 6. The comparator schematic diagram
Fig. 7. Simulation results of input offset voltage of comparator
Fig. 8. Vernier TDC structural diagram
Fig. 9. The delay cell circuit
Fig. 10. Delay time for different temperatures and different bias voltages
Fig. 11. The schematic block diagram of TDC circuit Testing system
Fig. 12. Test sequence diagram
Fig. 13. Coarse counting test results at room temperature and low temperature
Fig. 14. Fine counting value at room temperature and low temperature test
Fig. 15. (a)Differential non-linearity,(b)integral non-linearity
Fig. 16. The output results of fine counting under different delay time
Model parameters | Unit | NMOS | PMOS |
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77 K | 300 K | 77 K | 300 K |
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Vth0 | V | 0.958 | 0.719 | -1.121 | -0.724 | μ0 | cm2/Vs | 1 370 | 434 | 564 | 172 | vsat | m/s | 9.59E4 | 7.47E4 | 9.61E4 | 3.81E4 | Rdsw | Ω-μm | 1 663.2 | 1 373.16 | 3 841.31 | 2 530.47 |
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Table 1. Extraction results of the MOSFET parameters
Gain | 77.99 dB |
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Delay Time | 10.01 ns | Resolution | 12 bits | Noise | 7.621v/sqrt(hz)@1MHz |
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Table 2. Comparator simulation results
Time interval/ns | Coarse counter (Binary output) | Fine counter (decimal output) |
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846 | 100 000 | 19 | 847 | 100 000 | 27 | 848 849 | 100 000 100 000 | 34 42 | 850 | 100 000 | 50 |
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Table 3. Vernier TDC simulated output
Performance parameter | This work | Raytheon[19] | Southeast University[20] |
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Technology | CSMC CMOS 0.5 μm | TSMC CMOS 0.18 μm | CSMC CMOS 0.5 μm |
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Temperature Resolution | 77 K 236.28 ps | 300 K 297.47 ps | 77 K 166.67 ps | 300K 0.8 ns | Dynamic Range | 12 Bits | 12 Bits | 12 Bits | 13 Bits | Supply Voltage | 5 v | 5 v | 1.8 V | 5 V |
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Table 4. Compare the performance parameters of this work and Raytheon at 300 K and 77 K