[2] Hammer P D, Smith W H. Conference on Imaging Spectrometry, Orlando FL, SPIE Conference Proceedings, 1995, 2480.
[3] Xiangli Bin, Gao Zhan, An Baoqing. Proc. SPIE, 1998, 3502: 30.
[6] Fulton T R, Naylor D A, Baluteau J P, et al. Proc. SPIE, 2008, 7010: 70102T-1.
[7] Yoshida J, Kawashim A T. Proc. SPIE, 2008, 7082: 1.
[8] Akihiko Kuze, Hiroshi Suto, Kei Shiomi. Proc. SPIE, 2009, 7474: 747401-1.
[9] Rafert J B, Holbert E, Newby H, et al. Proc. SPIE, 1992, 1575: 263.
[10] Lucey P G, Horton K, Rafert J B, et al. Proc. SPIE, 1993, 1937: 130.
[11] Xilinx. Virtex-5 Integrated Endpoint Block for PCI Express Designs July 31, 2008.
[12] Howard W. Johnson Martin Graham High-Speed Digital Design Prentice Hall. 2000.
[13] ML507/506/507 PCIe X1 Endpoint Plus Design Creation Using ISE and CORE Generator 11. 1. May 2009.
[14] ML507/506/507 Getting Started Tutoria. June 18, 2009.
[15] Xilinx. Virtex-5 ML507/506/507 Reference Design June 29, 2008.
[16] Micron DDR2 SDRAM Small-Outline DIMM 256MB, 512MB, 1GB(X64, DR) 200-pin DDR2 SODIMM Feature. Micron Technology, Inc, 2006.