• Microelectronics
  • Vol. 53, Issue 3, 444 (2023)
CHEN Kairang1, WANG Bing1, WANG Youhua2, and YANG Yujun1
Author Affiliations
  • 1[in Chinese]
  • 2[in Chinese]
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    DOI: 10.13911/j.cnki.1004-3365.230032 Cite this Article
    CHEN Kairang, WANG Bing, WANG Youhua, YANG Yujun. A 14 bit Asynchronous Two-Stage Pipelined-SAR Analog to Digital Converter Technology[J]. Microelectronics, 2023, 53(3): 444 Copy Citation Text show less
    References

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    [2] ELSHATER A, LEE C Y, VENKATACHALA P K, et al. A 10 mW 16 b 15 MS/s two-step SAR ADC with 95 dB DR using dual-deadzone ring-amplifie [J]. IEEE Journal of Solid-State Circuits, 2019, 54(12): 3410-3420.

    [3] SONG Y, CHAN C H, ZHU Y, et al. A 125-MHz bandwidth 77-dB SNDR SAR-assisted noise shaping pipeline ADC [J]. IEEE Journal of Solid-State Circuits, 2020, 55(2): 312-321.

    [4] ROH Y J, CHANG D J, RYU S T. A 40-nm CMOS 12b 120-MS/s nonbinary SAR-assisted SAR ADC with double clock-rate coarse decision [J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2020, 67(12): 2833-2837.

    [5] LI H X, MADDOX M, COLN M C W, et al. A signal-independent background-calibrating 20 b 1 MS/s SAR ADC with 03 ppm INL [C] // IEEE ISSCC. San Francisco, CA, USA. 2018: 242-243.

    [6] FAN H, WANG Y N, WEI Q, et al. Capacitor recombination algorithm combined with LMS algorithm in 16-bit SAR ADC with redundancy [J]. Circuits Syst Signal Process, 2023, 42: 3181-3199.

    [7] SABERI M, LOTFI R. Segmented architecture for successive approximation analog to digital converters [J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2014, 22(3): 593-606.

    [8] PALUMBO G, PAPPALARDO D. Charge pumps: An overview on design strategies and topologies [J]. IEEE Circuits and Systems Magazine, 2010, 10(1): 31-45.

    [9] ZHANG D, BHIDE A, ALVANDPOUR A. A 53-nW 91-ENOB 1-kS/s SAR ADC in 013-μm CMOS for medical implant devices [J]. IEEE Journal of Solid-State Circuits, 2012, 47(7): 1585-1593.

    [10] WU C, YUAN J. A 12-bit, 300-MS/s single-channel pipelined-SAR ADC with an open-loop MDAC [J]. IEEE Journal of Solid-State Circuits, 2019, 54(5): 1446-1454.

    [11] JIANG W N, ZHU Y, ZHANG M L, et al. A temperature-stabilized single-channel 1-GS/s 60-dB SNDR SAR-assisted pipelined ADC with dynamic Gm-R-based amplifier [J]. IEEE Journal of Solid-State Circuits, 2020, 55(2): 322-332.

    [12] NI M, WANG X, LI F L, et al. A 13-bit 3125-MS/s pipelined SAR ADC with open-loop integrator-based residue amplifier and gain-stabilized integration time generation [J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2021, 29(7): 1416-1427.

    [13] YOON H C, LEE C, KIM T W, et al. A 65-dB-SNDR pipelined SAR ADC using PVT-robust capacitively degenerated dynamic amplifier [J]. IEEE Journal of Solid-State Circuits, 2023, 58(4): 961-971.

    CHEN Kairang, WANG Bing, WANG Youhua, YANG Yujun. A 14 bit Asynchronous Two-Stage Pipelined-SAR Analog to Digital Converter Technology[J]. Microelectronics, 2023, 53(3): 444
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