A 12-bit 45 GSPS digital-to-analog converter (DAC) in 013 μm SiGe BiCMOS technology is described Firstly this paper presents an evaluation of the technology constraints on the design of low latency time and high conversion rate for DAC. In order to achieve low latency and high speed, a special low latency architecture and current-mode logic (CML) have been used. And the introduction of innovative output modes bypassing the limits of sin(x)/x found in most DACs, and extending significantly DAC linearity. And architectural breakthrough, minimizing capacitive and inductive parasitics on critical nodes, allowed an extension of DAC usable output bandwidth up to 59 GHz. The converter has been fabricated, and test results showed that, at 45 GHz guaranteed conversion rate, the latency time is less than 35 clock cycles. Spurious free dynamic range (SFDR) for the described converter is 57 dBc at a clock rate of 45 GHz and an output frequency of 4455 GHz.