A Clock Data Recovery Circuit with Adaptive Loop Bandwidth Adjustment

CHANG Cheng; WEI Baolin; WEI Xueming; HOU Lingli; XU Weilin

doi:10.13911/j.cnki.1004-3365.210392

[1] KIM H R,LEE J Y,LEE J S,et al. A 6.4-11 Gb/s wide-range referenceless single-loop cdr with adaptive JTOL ［J］. IEEE Sol Sta Circ Lett, 2020(3): 470-473.

[2] SONNTAG J L, STONICK J. A digital clock and data recovery architecture for multi-gigabit/s binary links ［J］. IEEE J Sol Sta Circ, 2006, 41(8): 1867-1875.

[3] WU G, HUANG D, LI J, et al. A 1-16 Gb/s all-digital clock and data recovery with a wideband high-linearity phase interpolator ［J］. IEEE Trans VLSI Syst, 2016, 24(7): 2511-2520.

[4] SABER S S, EHSANIAN M. A linear high capture range CDR with adaptive loop bandwidth for SONET application ［C］// IEEE 29th ICM. Beirut, Lebanon. 2017: 1-4.

[5] RODONI L, VON BUREN G, HUBER A, et al. 5.75 to 44 Gb/s quarter rate CDR with data rate selection in 90 nm bulk CMOS ［J］. IEEE J Sol Sta Circ, 2009, 44(7): 1927-1941.

[6] ZHAO T, GAI W, TANG L, et al. A speculative clock and data recovery architecture for multi-gigabit/s series links ［C］// IEEE Int Conf EDSSC. Hongkong, China. 2016: 191-194.

[7] YU C, SA E, JIN S, et al. A 6.5-12.5-Gb/s half-rate single-loop all-digital referenceless CDR in 28-nm CMOS ［J］. IEEE J Sol Sta Circ, 2020, 55(10): 2831- 2841.

[8] PARK K, BAE W, LEE J, et al. A 6.7-11.2 Gb/s, 2.25 pJ/bit, single-loop referenceless CDR with multi-phase, oversampling PFD in 65-nm CMOS ［J］. IEEE J Sol Sta Circ, 2018, 53(10): 2982-2993.

[9] HUANG S, CAO J, GREEN M M. An 8.2 Gb/s-to-10.3 Gb/s full-rate linear referenceless CDR without frequency detector in 0.18 μm CMOS ［J］. IEEE J Sol Sta Circ, 2015, 50(9): 2048-2060.

[10] KWAK Y H, KIM Y, HWANG S, et al. A 20 Gb/s clock and data recovery with a ping-pong delay line for unlimited phase shifting in 65 nm CMOS process ［J］. IEEE Trans Circ & Syst I: Regu Pap, 2013, 60(2): 303-313.