A Fully Integrated 8 bit 216 GS/s SAR ADC

WU Qi; ZHANG Runxi; SHI Chunqi

doi:10.13911/j.cnki.1004-3365.210025

[1] LOCKIE D, PECK D. High-data-rate millimeter-wave radios ［J］. IEEE Microwave Mag, 2009, 10(5): 75-83.

[2] ULLAH H, TAHIR F A, AHMAD Z. A dual-band hexagon monopole antenna for 28 and 38 GHz millimeter-wave communications ［C］ // IEEE Int Symp Anten Nat Radio Sci Meet. Boston, MA, USA. 2018: 1215-1216.

[3] CHEN Q, PENG X, PENG K, et al. Dynamicbandwidth control MAC protocol for CWPAN/IEEE 80211aj networks ［C］ // IEEE Global Commun Conf. Austin, TX, USA. 2014: 4726-4731.

[4] JAVED A R, SCHEYTT J C, KRISHNEGOWDA K, et al.System design of a mixed signal transceiver using a linear ultra-broadband analog correlator for the receiver baseband designed in 130 nm SiGe BiCMOS technology ［C］ // IEEE Eurocon Int Conf Smart Tech. Ohrid, Macedonia. 2017: 228-233.

[5] OKADA K, KONDOU K, MIYAHARA M, et al. Full four-channel 63-Gb/s 60-GHz CMOS transceiver with low-power analog and digital baseband circuitry ［J］. IEEE J Sol Sta Circ, 2013, 48(1): 46-65.

[6] MIKI T, OZEKI T, NAKA J. A 2-GS/s 8-bit time- interleaved SAR ADC for millimeter-wave pulsed radar baseband SoC ［J］. IEEE J Sol Sta Circ, 2017, 52(10): 2712-2720.

[7] LI D, ZHU Z, DING R, et al. A 10-bit 600-MS/s time-interleaved SAR ADC with interpolation-based timing skew calibration ［J］. IEEE Trans Circ Syst II: Expr Bri, 2019, 66(1): 16-20.

[8] REYES B T, BIOLATO L, GALETTO A C, et al. An energy-efficient hierarchical architecture for time- interleaved SAR ADC ［J］. IEEE Trans Circ Syst I: Regu Pap, 2019, 66(6): 2064-2076.

[9] REYES B T, BIOLATO L, GALETTO A C, et al. A 4 GS/s 8-bit SAR ADC with an energy-efficient time-interleaved architecture in 130 nm CMOS ［C］ // CAE. Buenos Aires, Argentina. 2020: 77-81.

[10] XU L,CHEN D. Accurate and efficient method of jitter and noise separation and its application to ADC testing ［C］ // IEEE 32nd VLSI Test Symp. Napa, CA, USA. 2014: 1-5.

[11] ZHONG N, ZHANG R X, SHI C Q, et al. A bandwidth-tracking self-biased 5-to-2800 MHz low-jitter clock generator in 55 nm CMOS ［C］ // IEEE APCCAS. Qingdao, China. 2018: 57-60.

[14] WEI H, ZHANG P, SAHOO B D, et al. An 8 bit 4 GS/s 120 mW CMOS ADC ［J］. IEEE J Sol Sta Circ, 2014, 49(8): 1751-1761.