• Microelectronics
  • Vol. 51, Issue 6, 889 (2021)
DENG Zhihao, CHENG Jianbing, LI Yingnan, ZHANG Cairong, and ZHOU Jiacheng
Author Affiliations
  • [in Chinese]
  • show less
    DOI: 10.13911/j.cnki.1004-3365.210033 Cite this Article
    DENG Zhihao, CHENG Jianbing, LI Yingnan, ZHANG Cairong, ZHOU Jiacheng. A New Fast Turn-Off ESD Power Clamp Circuit[J]. Microelectronics, 2021, 51(6): 889 Copy Citation Text show less
    References

    [1] LANGGUTH G, RUSS C, SOLDNER W, et al. ESD challenges in advanced CMOS systems on chip [C] // IEEE ICICDT. Grenoble, France. 2010: 29-34.

    [2] NARITA K, OKUSHIMA M. A variable VH combined power clamp for system level ESD/surge immunity enhancement with low leakage [C] // 41st Annual EOS/ESD Symp. Riverside, CA, USA. 2019: 1-6.

    [3] ELGHAZALI M, SACHDEV M, OPAL A. A low-leakage, hybrid ESD power supply clamp in 65 nm CMOS technology [C] // Proceed IEEE CICC. San Jose, CA, USA. 2014: 1-4.

    [4] LU G, WANG Y, CAO J, et al. Design and verification of a novel multi-RC-triggered power clamp circuit for on-chip ESD protection [C] // 35th EOS/ESD. Las Vegas, NV, USA.2013: 1-7.

    [5] CHEN J, KER M. Design of power-rail ESD clamp with dynamic timing-voltage detection against false trigger during fast power-on events [J]. IEEE Trans Elec Dev, 2018, 65(3): 838-846.

    [6] CHEN J, KER M. Power-rail ESD clamp circuit with polysilicon diodes against false trigger during fast power-on events [C] //40th EOS/ESD. Reno, NV, USA. 2018: 1-7.

    DENG Zhihao, CHENG Jianbing, LI Yingnan, ZHANG Cairong, ZHOU Jiacheng. A New Fast Turn-Off ESD Power Clamp Circuit[J]. Microelectronics, 2021, 51(6): 889
    Download Citation