Efficient fault tolerant reversible Hamming code encoding and detection circuits

Xue-mei QI; Fu-long CHEN; Yong-long LUO

doi:10.3969/j.issn.1007-5461. 2013.05.013

[1] Landauer R. Irreversibility and heat generation in the computing process ［J］. IBM J. Res. Develop., 1961, 5(2): 183-191.

[2] Bennett C H. Logical reversibility of computation ［J］. IBM J. Res. Develop., 1973, 17(6): 525-532.

[3] Haghparast M. Design and implementation of nanometric fault tolerant reversible BCD adder ［J］. Aust. J. Basic & Appl. Sci., 2011, 5(10): 896-901.

[4] Haphparast M, Mohammad M, Navi K, et al. Optimized reversible multiplier circuit ［J］. J. Circuit Syst. Comp., 2009, 18(2): 311-323.

[5] Mohammadi M, Eshghi M. On figures of merit in reversible and quantum logic designs ［C］. Quant. Info. Proc., 2009, 8(4): 297-318.

[6] Islam M S, Begum Z. Reversible logic synthesis of fault tolerant carry skip BCD adder ［J］. J. of Bangladesh Academy of Sci., 2008, 32(2): 193-200.

[8] Haghparast M. Design and implementation of nanometric fault tolerant reversible BCD adder ［J］. Aust. J. Basic & Appl. Sci., 2011, 5(10): 896-901.

[9] Haghparast M, Dastan F. A novel nanometric fault tolerant reversible divider ［J］. Int. J. Phys. Sci., 2011, (24): 5671-5681.

[10] Akbar E P A, Haghparast M, Navi K. Novel design of a fast reversible Wallace sign multiplier circuit in nanotechnology ［J］. Microelectron. J., 2011, 42(8): 973-981.

[11] Qi Xuemei, Chen Fulong, Zuo Kaizhong, et al. Design of fast fault tolerant reversible signed multiplier ［J］. Int. J. Phy. Sci., 2012, 7(17): 2506-2514.

[12] Haghparast M, Navi K. Novel reversible fault tolerant error coding and detection circuits ［J］. Int. J. Quant. Inform., 2011, 9(2):723-738.