A Pruned Neural Network Algorithm for High Precision SAR ADC Calibration

WANG Liang; DENG Honghui; CHEN Hao; YIN Yongsheng

doi:10.13911/j.cnki.1004-3365.zjea025

[3] MCNEILL J A, CHAN K Y, COLN M C W, et al. All-digital background calibration of a successive approximation ADC using the “split ADC” architecture ［J］. IEEE Trans Circ Syst I: Reg Pap, 2011, 58(10): 2355-2365.

[4] SUN J, ZHANG M L, QIU L, et al. Background calibration of bit weights in pipelined-SAR ADCs using paired comparators ［J］. IEEE Trans VLSI Syst, 2020, 28(4): 1074-1078.

[5] XU H, WANG L, YUAN R, et al. A/D converter background calibration algorithm based on neural network ［C］// ICET. Chengdu, China. 2018: 1-4.

[6] DENG H, HU Y, WANG L. An efficient background calibration technique for analog-to-digital converters based on neural network ［J］. Integr VLSI J, 2020, 74(4): 63-70.

[7] SUN L, DAI Q, LEE C, et al. Analysis on capacitor mismatch and parasitic capacitors effect of improved segmented-capacitor array in SAR ADC ［C］// 3rd Int Symp IITA. Nanchang, China. 2009: 280-283.

[8] GUAN R, XUE J F, YANG C, et al. A 16-bit 1 MS/s SAR ADC with foreground digital-domain calibration ［J］. IET Circ Devices & Syst, 2018, 12(4): 505-513.

[9] LIU W, HUANG P, CHIU Y. A 12-bit 45-MS/s 3-mW redundant successive approximation register analog-to- digital converter with digital calibration ［J］. 2011, 46(11): 2661-2672.

[10] WANG G, KACANI F, CHIU Y. IRD digital background calibration of SAR ADC with coarse reference ADC acceleration ［J］. IEEE Trans Circ Syst II: Expr Bri, 2014, 61 (1): 11-15.

[11] CHEN L, MA J, SUN N. Capacitor mismatch calibration for SAR ADCs based on comparator metastability detection ［C］// IEEE ISCAS. Melbourne, VIC, Australia. 2014: 2357-2360.

[12] XU R, LIU B, YUAN J. Digitally calibrated 768-ks/s 10-b minimum-size SAR ADC array with dithering ［J］. IEEE J Sol Sta Circ, 2012, 47(9): 2129-2140.