• Chinese Physics B
  • Vol. 29, Issue 10, (2020)
Hui-Fang Xu, Xin-Feng Han, and Wen Sun
Author Affiliations
  • Institute of Electrical and Electronic Engineering, Anhui Science and Technology University, Fengyang 233100, China
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    DOI: 10.1088/1674-1056/ab9c06 Cite this Article
    Hui-Fang Xu, Xin-Feng Han, Wen Sun. Design and investigation of dopingless double-gate line tunneling transistor: Analog performance, linearity, and harmonic distortion analysis[J]. Chinese Physics B, 2020, 29(10): Copy Citation Text show less
    Structure of devices of (a) PT−DLTFET, (b) LT−DLTFET, and (c) M−LT−DLTFET.
    Fig. 1. Structure of devices of (a) PTDLTFET, (b) LTDLTFET, and (c) MLTDLTFET.
    Plot of energy varying with distance for M−LT−DLTFET along (a) A–A’ direction, and (b) B–B’ direction under on-state condition, (c) plots of electron and hole concentrations varying with top-bottom distance along B–B’ direction under on-state condition.
    Fig. 2. Plot of energy varying with distance for MLTDLTFET along (a) A–A’ direction, and (b) B–B’ direction under on-state condition, (c) plots of electron and hole concentrations varying with top-bottom distance along B–B’ direction under on-state condition.
    (a) Electric field varying with distance along cutline A–A’, (b) electron current density varying with distance along cutline A–A’, (c) transfer characteristics, and (d) extracted SS varying with Ids for the devices.
    Fig. 3. (a) Electric field varying with distance along cutline A–A’, (b) electron current density varying with distance along cutline A–A’, (c) transfer characteristics, and (d) extracted SS varying with Ids for the devices.
    Plots of energy varying with distance at different values of LTGS (a) along cutline A–A’ when Vgs is fixed at 0.2 V, (b) along cutline A–A’ when Vgs is fixed at 1 V, (c) along cutline B–B’ when Vgs is fixed at 0.2 V, and (d) along cutline B–B’ when Vgs is fixed at 1 V.
    Fig. 4. Plots of energy varying with distance at different values of LTGS (a) along cutline A–A’ when Vgs is fixed at 0.2 V, (b) along cutline A–A’ when Vgs is fixed at 1 V, (c) along cutline B–B’ when Vgs is fixed at 0.2 V, and (d) along cutline B–B’ when Vgs is fixed at 1 V.
    (a) Transfer characteristics, and (b) electric fields varying with distance along A–A’ direction for proposed device with different distances between source and top-gate electrode.
    Fig. 5. (a) Transfer characteristics, and (b) electric fields varying with distance along A–A’ direction for proposed device with different distances between source and top-gate electrode.
    (a) Transfer characteristics, and (b) energy varying with distance along A–A’ direction for proposed device with different distances between top-gate and drain electrode.
    Fig. 6. (a) Transfer characteristics, and (b) energy varying with distance along A–A’ direction for proposed device with different distances between top-gate and drain electrode.
    Plots of energyvarying with distance along (a) A–A’, and (b) C–C’ direction for proposed device with different distances between bottom-gate and drain electrode.
    Fig. 7. Plots of energyvarying with distance along (a) A–A’, and (b) C–C’ direction for proposed device with different distances between bottom-gate and drain electrode.
    Plots of IdsversusVgs for M−LT−DLTFET with metal at different positions along (a) x direction and (b) y direction, (c) for different work functions of metal.
    Fig. 8. Plots of IdsversusVgs for MLTDLTFET with metal at different positions along (a) x direction and (b) y direction, (c) for different work functions of metal.
    Plots of (a) gm, (b) Cgd, (c) CggversusVgs for three devices.
    Fig. 9. Plots of (a) gm, (b) Cgd, (c) CggversusVgs for three devices.
    RF parameters of (a) ft, (b) GBP, and (c) TFP for three devices.
    Fig. 10. RF parameters of (a) ft, (b) GBP, and (c) TFP for three devices.
    Plots of (a) gm2, and (b) gm3versusVgs for three devices.
    Fig. 11. Plots of (a) gm2, and (b) gm3versusVgs for three devices.
    Linearity parameters of (a) VIP2, (b) VIP3, (c) IIP3, and (d) IMD3 for three devices.
    Fig. 12. Linearity parameters of (a) VIP2, (b) VIP3, (c) IIP3, and (d) IMD3 for three devices.
    Plots of (a) HD2, and (b) HD3versusVgs for three devices.
    Fig. 13. Plots of (a) HD2, and (b) HD3versusVgs for three devices.
    ParameterSymbolPTDLTFETLTDLTFETMLTDLTFET
    Top gate lengthLTG55 nm55 nm55 nm
    Bottom gate lengthLBG55 nm50 nm50 nm
    Source lengthLS20 nm20 nm20 nm
    Drain lengthLD20 nm20 nm20 nm
    Distance between top gate and source electrodeLTGS5 nm5 nm5 nm
    Distance between top gate and drain electrodeLTGD10 nm10 nm10 nm
    Distance between bottom gate and drain electrodeLBGD10 nm20 nm20 nm
    Oxide layer thicknessTOX3 nm3 nm3 nm
    Ge body thicknessTGe10 nm10 nm10 nm
    Top gate work functionWKTG4.2 eV3.9 eV3.9 eV
    Bottom gate work functionWKBG4.2 eV4.6 eV4.6 eV
    Metal work functionWKM3.9 eV
    Source electrode work functionWKS5.9 eV5.9 eV5.9 eV
    Drain electrode work functionWKD3.9 eV3.9 eV3.9 eV
    Table 1. Material parameters and dimensions of devices.
    ParameterPT_DLTFETLT_DLTFETM_LT_DLTFET
    Ion/(A/μm)1.90117×10−64.44004×10−61.14652×10−5
    Ion/Ioff4.19×1089.81×1081.48×109
    Iamb/(A/μm)5.01×10−154.69×10−154.67×10−15
    SSavg/(mV/dec)72.5244.0734.15
    SSmin/(mV/dec)27.4729.3626.23
    Vth/V0.340.20.16
    Table 2. Comparison of DC parameter among devices.
    Hui-Fang Xu, Xin-Feng Han, Wen Sun. Design and investigation of dopingless double-gate line tunneling transistor: Analog performance, linearity, and harmonic distortion analysis[J]. Chinese Physics B, 2020, 29(10):
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