There are many modulation schemes that have been studied for different applications in optical communication systems. Non-return-to-zero (NRZ) is widely used due to its simplicity and cost-effectiveness. However, the rapid growth of data traffic has motivated the utilization of other modulation formats with better spectral efficiency. Among them, 4-level pulse amplitude modulation (PAM4) has been adopted for high data rate standards because it doubles the transmission bit rate at the same bandwidth, compared to NRZ binary modulation. The spectral efficiency of the PAM4 modulation scheme comes at the cost of more than a 9 dB SNR penalty due to the reduction of the PAM4 eye height with respect to NRZ. Therefore, PAM4 transmitters are required to deliver a larger output voltage swing to satisfy the same bit error rate (BER) of NRZ. This work demonstrates a dual-mode NRZ/PAM4 driver circuit for high current directly modulated lasers with minimum hardware overhead.

The design of a laser diode driver (LDD) is considered to be one of the most challenging parts among the whole optical transceiver due to the following reasons: firstly, LDDs must deliver large output currents at high speeds, corresponding to small driving signals. For a large output current, a high driving signal and/or wider output transistors are necessary. The high input capacitance of the wide output transistors dramatically decreases the driver operating speed. Therefore, pre-driver stages must precede the output driver so as to deliver a large output current while displaying a small input capacitance^[1].

Secondly, the LDD circuit must employ an output back termination to absorb signal reflections from the laser side when driving commercial laser diodes (LDs)^{[2, 3]}, due to the imperfect match between the laser impedance and the printed circuit board (PCB) transmission line (TL) impedance. The simplest way to achieve that is to use passive on-chip back termination resistors across the driver output terminals^[4-8], as shown in Fig. 1(a). If the value of this resistor exactly equals the TL impedance, the driver will completely absorb all reflected pulses without any further re-reflections to the laser side. However, the modulation current range is reduced by 50% as half of it is lost in the back-termination resistor. Another method, so-called active back termination (ABT)^{[2, 3, 9-12]}, can absorb the loading reflections without compromising the modulation current range. In this method, shown in Fig. 1(b), is connected between the driver output and the output of a scaled-down replica stage, used to generate an internal estimate of the driver output voltage. Due to the external dc offset of laser diodes, a dc offset cancellation loop circuit is needed to guarantee perfect matching between the dc output voltages of the ABT and the driver^{[9, 12]}. Under normal operation, no power is wasted in , and the modulation current exactly equals the driver tail current. However, this technique needs additional circuitry with extra power and area, and its functionality is degraded at high speeds. Therefore, it is not adopted in this design, and passive back termination resistors are mainly utilized to reduce the physical layout area.

Thirdly, LDDs are power-hungry circuits, especially at high output currents. Therefore, it is highly recommended to reduce the power dissipation of driver circuits to enable the realization of an air-cooled system and simplify the chip packaging^[13].

Recently, several attempts with excellent results were reported for high current NRZ driver ICs implemented in various high-speed technologies. Using SiGe BiCMOS technology, an 80 mA laser driver operating at 1.25 Gbps, an 80 mA variable data rate driver (155 Mb/s to 4.25 Gbps), and a 50 Gbps optical transmitter with 40 mA output current were reported in Refs. [14, 10, 6], respectively. In pHEMT technology, a 10 Gbps modulator driver with 1.8 V_pp single-ended output voltage and a 100 mA 10 Gbps laser driver with active back termination were proposed in Refs. [15, 9], respectively. On the other hand, the CMOS process can still compete to implement such circuits using broadband techniques like inductive peaking^{[3, 5, 12, 16-18]} and negative impedance converters^{[4, 12, 19]}. These techniques improve the speed, especially when a high driving current capability is required. PAM4 driver ICs were also reported for low current vertical-cavity surface-emitting lasers (VCSELs), at 90 Gbps^[20] and 56 Gbps^[21] in SiGe BiCMOS technology and 25 Gbps in 90 nm CMOS^[22], and high current distributed feedback (DFB) laser, at 30 Gbps in the 65 nm CMOS process^[11].

This paper reports on the design, fabrication, and testing of a 15 Gbps-NRZ, 30 Gbps-PAM4 high current LDD implemented in a 0.15-µm GaAs pHEMT technology. The proposed driver is experimentally verified using a wire-bonded chip-on-board assembly. It can deliver a maximum modulation current of 120 mA to 25-Ω load.

The proposed LDD is designed and fabricated using the 0.15-µm GaAs E-mode pHEMT process. Besides the 0.15-µm E-mode transistor, the process also includes the following elements: PN junction diodes; 50 Ω/sq. tantalum nitride (TaN) thin-film resistors; 150 Ω/sq. active layer resistors; MIM capacitors with a density of 400 pF/mm²; round and square inductors; and two metal layers for interconnecting.

In Fig. 2(a), the variations of the drain current ( ) and transconductance ( ) with gate–source voltage ( ) of the pHEMT are shown. The maximum is 1000 mS/mm. The drain current is about 430 mA/mm at = 0.9 V. The typical threshold voltage ( ) is 0.3 V. The characteristics of unity gain cutoff frequency ( ) in terms of is depicted in Fig. 2(b). It can be seen that the maximum is about 110 GHz. These results are promising enough to produce high-speed drivers that can deliver large output currents.

The LDD architecture consists of two two-stage slices, as shown in Fig. 3. Each slice includes a pre-driver followed by an output driver, as schematically depicted in Fig. 4. The circuit is designed in a differential current mode logic (CML) topology due to its high speed and excellent immunity to switching noise, as the supply current is maintained relatively constant^[1]. The circuit is powered using a single negative supply voltage ( ) as shown in Fig. 4. A 100-Ω on-chip resistor is used across the output of each slice, producing a 50-Ω output back-termination impedance. Each slice presents a 50-Ω single-ended input impedance using on-chip resistors. The maximum tail currents, and , are 120 and 60 mA, and the corresponding output currents of slice I and slice II, when driving 25-Ω loads, are 80 and 40 mA, respectively. In this design, the cascode current mirror circuits are used to accurately adjust the tail currents due to their low systematic gain-error^[23]. They also introduce a small output conductance, which improves the common-mode rejection ratio, and consequently, the driver circuit becomes less sensitive to common-mode noise.

The proposed driver can be used in two different functions: firstly, as illustrated in Fig. 3(a), each slice can operate as a stand-alone 15 Gbps-NRZ LDD with a maximum output current of 80 and 40 mA for slice I and slice II, respectively, when driving 25-Ω lasers. In this case, the NRZ input data is connected to the enabled slice while the other slice is deactivated. The output current can be boosted to 120 mA by simultaneously enabling the two slices and driving them with identical input signals.

Secondly, the circuit can work as a 30 Gbps (15 Gbaud/s) PAM4 LDD by combining the two 15 Gbps-NRZ drivers, as shown in Fig. 3(b). According to the possibilities of the most significant bit ( ) and the least significant bit ( ), 00, 01,10, or 11, the output modulation current will be 0, 40, 80, or 120 mA, respectively. With the PAM4 modulation scheme, the transmission bit data rate is doubled at the same bandwidth compared to NRZ binary modulation.

Fig. 5 illustrates a simple model of an LDD with passive back termination and the LD, where the LDD and the LD are connected using a wire-bonded chip-on-board assembly. Here, is the parasitic output capacitance of the driver, is the passive back termination resistor, L is the bonding wire inductance, , and are the parasitic capacitance and the equivalent input resistance of the LD, respectively. is the tail current of the driver and is the modulation current of the LD. equals 25 Ω and is assumed to be as low as 0.2 pF. The PCB trace is a 25-Ω microstrip TL (l = 5 mm), designed using Rogers material, which has a relative dielectric constant ( ) of 3.48. In this case, only degrades the matching at the laser side, especially at high frequencies. Fig. 6 shows the 25-Ω curves, simulated at the LD side, at different and L values. Without , will exactly equal , but the maximum in the frequency range from 0 to 15 GHz ( ) is about −0.03 dB, which seriously degrades the waveform fidelity. At perfect matching ( 25 Ω), is reduced to 0.5 while a better performance is obtained especially at low L values. If is somewhat chosen to be greater than 25 Ω, will be larger than 0.5 ( equals 0.667 and 0.75 when 50 and 75 Ω, respectively) on the cost of degrading at low frequencies. However, performance at high frequencies may not be significantly impacted (or even improved) where the driver output impedance, parasitic capacitances, and inductances play a significant role^[24]. When L = 0, 0.5, and 1 nH, values at 25, 50, and 75 Ω are (–12.9, –4, and –1.2 dB), (–7.4, –8.2, and –2.1 dB), and (–4.9, –6, –2.4 dB), respectively. At L = 0 nH, at 25 Ω is much lower than at 50 or 75 Ω. Whereas, when L = 0.5 nH or 1.0 nH, values at 50 and 75 Ω are better than the values obtained at perfect matching ( 25 Ω). These simulation results demonstrate that LDDs must employ output transmission line back-termination to absorb signal reflections from the laser side. A larger values could be used to reduce the waste in ^{[8, 24]}, especially when a good matching at the laser side is guaranteed. In the proposed design, a 50-Ω passive on-chip back termination resistor is utilized to balance between suppressing reflections and the loss in modulation current. It is worth mentioning that the TL is preferred to be as short as possible to reduce the insertion loss and propagation delay across it.

For any CML circuits in cascade, the single-ended output voltage swing is relatively small, less than peak-to-peak^[25], to keep the transistors of the differential pairs in saturation, and consequently guarantee a high-speed operation. In the proposed circuit, the maximum single-ended output voltage of the output driver ( ) equals 3 V_pp when the output current is 120 mA. Therefore, a series resistor ( ) is utilized in the pre-driver stage as a level shifter that reduces the common-mode output voltage at from ( ) to ( ). Consequently, the output voltage swing of the output driver stage can be higher than . An alternative solution to provide a high output voltage is to use level shifter stages, connecting between the pre-driver and the output driver^{[7, 13, 26]}. Despite the buffering effect introduced by these stages, they significantly increase the power consumption of the driver circuit.

Focusing on slice I and considering the case at which the two slices are enabled to drive a 25-Ω load, the following formulas must be satisfied to keep (M_1a–M_1b), (M_2a–M_2b), and the tail current sources and in saturation region:

 (1)

 (2)

 (3)

 (4)

where , , , and are the single-ended input voltage, the DC common-mode input voltage, the single-ended output voltage of the pre-driver, and the output driver, respectively. and are the minimum required voltage to maintain the cascode current mirrors in saturation. and are the required gate–source voltages to make and equally divided between ( and ) and ( and ), respectively. The cascode current mirrors are sized such that and are less than 0.7 and 0.9 V, respectively. To operate near the maximum , and are assumed to be higher than or equal to 0.6 V, drain current density ≥ 170 mA/mm.

By substituting into Eq. (2) with the maximum possible , which is 3 V_pp when both slices are simultaneously enabled, and of 0.3 V, we get that must be higher than 2.7 V. From Eq. (3), must be 1.3 V above the level. If , , and are set to 2.8, –3.8, and –5.2 V, respectively, must be less than 1.3 V, as derived from Eq. (1). at which complete current switching in both the pre-driver and the output driver stages is required to be as low as 300 mV_pp, and thereby must be less than 1.15 V_pp.

In order to achieve complete current switching in the output driver stage, a large input swing ( ) and/or wide transistors (M_2a–M_2b) are required. However, the circuit bandwidth is degraded as increases due to the corresponding large input capacitance. On the other hand, increasing the output swing of the pre-driver ( ), by increasing and/or , results in higher power dissipation and/or bandwidth degradation, respectively. Thus, the final choices of , , and are determined after a set of iterations to achieve complete switching at acceptable speed and power consumption.

The small-signal equivalent half-circuit of the proposed driver and a 25-Ω laser diode is shown in Fig. 7, when only slice I is enabled. , , and are the gate–source, gate–drain, and drain–bulk capacitances of M_i. is the transconductance of M_i. and are the single-ended input resistance and capacitance of the pre-driver stage. and are the resistive loads of the pre-driver and output driver, respectively. and represent the equivalent input resistance and the parasitic capacitance of the laser diode, and they account for 25 Ω and 0.5 pF, respectively. As the frequency response of the circuit is dominated by the output driver capacitances, the miller approximation capacitance of is considered for simplicity, thereby and , where is the pre-driver voltage gain. The small-signal transfer function of the circuit can be expressed as;

 (5)

where

 (6)

 (7)

and represent the parallel combination of ( and ) and ( and ), respectively. For , which is generally achieved for small values of , the transfer function shows an overdamped behavior with three real left half-plane (LHP) poles;

 (8)

 (9)

 (10)

The numerator of Eq. (5) shows only one zero located at , which is substantially larger than the system poles. Generally, is larger than , and therefore . Moreover, at 0, is much lower than , and the small-signal bandwidth (BW) approximately equals . Initially, is assumed to be zero, and the values of , , and are chosen such that the small-signal BW is higher than 5 GHz, while complete current switching is achieved. Then, the BW will be boosted by adjusting . Fig. 8 shows the BW dependence on and at different . The size of the pre-driver differential pair ( ) is chosen to guarantee complete switching of corresponding to the 300 mV_pp single-ended input signal. The value of is adjusted such that the voltage drop across it is about 2.8 V, as derived from Eq. (2). The shaded areas in Fig. 8 represent the accepted values of and at which the output voltage of the output driver ( ) exceeds 1.96 V_pp (98% of passes through the ON transistor) when the input voltage equals 300 mV_pp (single-ended). At 15 mA, the highest BW in the shaded area, where 1.96 V_pp, exceeds 5 GHz (about 5.6 GHz), and this occurs at 235 µm and 52.2 Ω. The parameters , , and are chosen to be 15 mA, 58 Ω (a little bit higher than 52.2 Ω to ensure that 1.96 V_pp at different processes and temperature corners), and 235 µm, respectively, as shown in Fig. 8(c). At this point, and equal 0.87 and 2 V_pp, respectively, and the small-signal BW is about 5.16 GHz.

Fig. 9(a) illustrates the dependence of BW and on , where is maintained constant at 0.87 V_pp ( 0.87/ ) and is chosen to achieve complete switching of through (M_1a–M_1b). At lower values of , is much lower than , and consequently, the BW is dominated by . However, as increases, and thereby increase accordingly. In this case, the pole introduced at the input of the pre-driver ( ) can no longer be ignored as it significantly degrades the circuit BW. So, at higher values, a little improvement in the BW is achieved on the cost of higher power dissipation and area for the pre-driver circuit.

The dc transfer characteristic curves that show the voltage variations of the pre-driver and output driver output nodes in terms of the fully differential input voltage are shown in Fig. 9(b). It is clear that complete current switching, in the output driver stage, occurs at a differential input voltage of about 500 mV_ppd (250 mV_pp single-ended).

In the proposed design, the input capacitance effect of the output driver is reduced by using cross-coupled neutralization capacitors. The impact of these capacitors on the poles locus is illustrated in Fig. 10(a), where is varied from 0 to 350 fF. The first pole (P₁) is not altered by changing as given in Eq. (8). As increases, the dominant pole (P₂) moves away from the origin, resulting in a higher bandwidth. Meanwhile P₃ moves towards the origin until reaching the break-out point, and then the two poles split out, producing an underdamped response. If is further increased above 300 fF, P₂ and P₃ become positive, and an unstable system is obtained. Fig. 10(b) shows the small-signal BW and the peaking in the magnitude response dependences on . For peaking-free frequency response, must be below 90 fF. Fig. 11 shows the magnitude and group delay (GD) responses of slice I at different values. The highest BW, without peaking, and the optimum GD response occurred exactly at 90 fF. However, the chosen value of must be below this bound to avoid any peaking in the magnitude response and large variances in GD when bonding wire inductance is accounted. In this design, a value of 65 fF satisfies this condition. At this point, equals approximately 126 % of and the input capacitance of the main driver is reduced by about 30%. Consequently, the small-signal of slice I is increased by 42.8% to reach 7.3 GHz.

Actually, the small-signal transfer function will be impacted in the existence of bonding wire inductance (L), which connects between the driver output and the LD. In this case, the system order is raised to five, and hence two additional complex conjugate poles are introduced. Fig. 12 shows the poles locus and the small-signal dependence on L, when 65 fF and L is swept from 0.1 to 3 nH. Whereas, the magnitude and group delay responses at different values of L is illustrated in Fig. 13. However, the dominant pole ( ) moves towards origin as L increases, the BW slightly increases, as L varies from 0 to 0.5 nH, due to the high-quality factor of the complex conjugate poles (P₄ and P₅) which introduces a peaking at their undamped natural frequency. If L is further increased above 0.5 nH, the BW decreases as the quality factor of (P₄ and P₅) decreases such that it is no longer able to compensate for the decrease in P₂, and thereby the BW is dominated by . Also, group delay variances across the frequency domain are observed when L > 0.5 nH. Therefore, the bonding wiring inductance must be as small as possible to avoid the previous effects.

Fig. 14 shows the simulated 15 Gbps single-ended output eye diagrams at different L values. The input pattern is 2⁷–1 pseudorandom bit sequence (PRBS) with a single-ended amplitude of 300 mV_pp. A well-behaved time response, without ringing, overshoots, or undershoots, is observed for L < 1 nH. The rise/fall times (20%–80%) at L = 0 nH equal 22/19.8 ps. At higher L values, the driver BW dramatically decreases, leading to higher rise/fall times and severe inter-symbol interference (ISI) as shown in Fig. 14(d).

The second slice is designed using the same previous procedure. With , , , , , and of 12 mA, 68.75 Ω, 233 Ω, 55 µm, 120 µm, and 30 fF, respectively, the small-signal bandwidth is about 8 GHz and the rise/fall times equal 16.5/15 ps.

Large signal S-parameters characterization of the driver is performed at an input signal level of 0.6 V_ppd (0.3 V_pp single-ended), and the results are presented in Fig. 15(a). The forward-path gain ( ) curves demonstrate that the large signal bandwidth of slice I and slice II are 10 and 11.15 GHz, respectively. The input return loss is better than 10 dB up to 20 GHz for both slices. The output return loss is better than 10 dB up to 13.2 GHz. It is worth mentioning that both slices are required to produce similar group delay responses in the band of interest to avoid distortions in the output PAM4 signal. Fig. 15(b) shows the simulated group delay of both slices. The low-frequency group delay is about 34.5 and 33.7 ps for the MSB (slice I) and LSB (slice II) paths, respectively, and the peak difference is only 2.8 ps at 20 GHz.

The time-domain analysis was also performed to demonstrate the large-signal capability of the proposed driver. In this analysis, a large signal model of the laser diode, shown in Fig. 16(a), is utilized. The model consists of a forward-biased PN junction diode (D₁) with its own parasitics ( and ), and the package parasitic elements, , , and ^{[27, 28]}. As most DFB lasers have a series resistance ( ) of approximately 5-Ω, a series matching resistor ( ) of 20-Ω is included in the laser package to provide a total input impedance of 25-Ω^{[24, 29]}. The laser diode threshold current ( ) and the forward voltage ( ) are assumed to be 10 mA and 1.4 V at 150 mA forward current, respectively. The I–V characteristic curve of D₁, given in Fig. 16(b), shows that 5 Ω, D₁ forward voltage ( ) is about 0.51 V at 1 mA forward current, and 1.4 V at 150 mA forward current, which matches the assumed laser diode characteristics. The laser diodes are often biased above to improve their speed^[24], and thereby D₁ is DC biased with 25 mA. The RF cathode terminal of the LD model is DC-coupled to the inverting output terminal of the LDD chip through a bonding wire inductance ( ) and a 25-Ω microstrip PCB TL, while the non-inverting terminal is loaded with a 25-Ω dummy resistor. The length of the TL is 5 mm, and it is designed using Rogers PCB which has 3.48.

The input pattern is a PRBS-7 signal with a single-ended amplitude of 300 mV_pp. The simulated single-ended output eye diagrams at the RF cathode terminal of the LD model are illustrated in Fig. 17. The eye diagrams are obtained at different data rates when either slice is enabled or both slices are simultaneously enabled and driven by identical input patterns. Clear output eye diagrams are obtained at speeds up to 15 Gbps. The amplitude of the output eye diagram and the corresponding output current amplitude are (2 V and 80 mA) for slice I, (1 V and 40 mA) for slice II, and (3 V and 120 mA) for both slices, respectively. The rise/fall times at 15 Gbps for slice I and II are 24.2/23.3 ps and 19.3/18.5 ps, respectively.

If a simple resistive load was used, the high-level of the output eye diagrams, which occurs at zero output current, would be zero. However, when interfacing the proposed LDD, which has a 50-Ω single-ended output back termination, with the forward-biased LD model given in Fig. 16, the high-level values are shifted down to approximately –0.5 V, as shown in Fig. 17. Also, the low-level values are shifted down by the same amount. The proposed driver offers a sufficient output voltage compliance range that allows DC-coupling to 25-Ω lasers with output current up to 120 mA. With –5.2 V, simulation results reveal that the minimum voltage needed at the output of the driver for proper operation, achieving fast complete current switching, is about –3.65 V. Therefore, the allowable headroom for the laser and its matching resistor equals 3.65 V when the laser anode terminal is grounded. If the laser anode terminal is powered from a positive supply voltage (V_DD), the output headroom will increase to V_DD + 3.65 V, at the cost of increasing the power dissipation.

Fig. 18 shows the output eye diagrams when the driver is used as a PAM4 transmitter at different data rates. A PRBS-7 pattern is applied to slice I while slice II is supplied with a one-bit delayed replica of the same pattern. Clear PAM4 eye diagrams are obtained at speeds up to 30 Gbps (15 Gbaud/s). The output voltage levels are –0.5, –1.5, –2.5, and –3.5 V, and consequently the peak-to-peak output voltage and current are 3 V and 120 mA, respectively.

The design reliability is verified by checking the circuit performance at different process corners, supply voltage (±10%), and temperatures (from –40 to 125 °C), (PVT analysis). The output eye diagram features, for slice I and slice II, at 15 Gbps are summarized in Table 1. The results demonstrate that the eye diagram features are almost acceptable.

The proposed driver is fabricated in a 0.15-µm GaAs E-mode pHEMT process. The chip occupies a total area of 0.7 × 1.3 mm². The die photograph and its corresponding bonding wire to a custom-designed Rogers PCB ( = 3.48) are shown in Fig. 19. Two pads are assigned for each output terminal of the driver to reduce the bonding wire inductance. Gold bonding wires with aa 25.4 µm diameter were used, and the output bonding wires' lengths are less than 0.8 mm. Using the rule of thumb of 1 nH/mm, the estimated output bonding wire inductance will be less than 0.4 nH. With this low bonding wire inductance, the circuit performance will not be substantially affected, as discussed in Section 3.2.

Low-dropout (LDO) regulators are used to generate the required supply voltage and biasing to the chip. The ground bounce noise caused by supply bonding wires is suppressed by using localized decoupling networks, consisting of ferrite beads and ceramic capacitors. These components are mounted near the chip on the bottom side of the evaluation board. Both of the input connectors and the output load are placed as near as possible to the chip to reduce the traces’ lengths. The input signals are AC coupled to the chip using 0.1 µF coupling capacitors. Each output terminal of the driver is DC coupled to a 25-Ω resistive load that is formed of two parallel-connected high-frequency 50-Ω resistors. The input traces are designed as 100-Ω differential transmission lines, while the output traces are considered as short interconnects due to the difficulty of designing 25-Ω PCB transmission lines. The electrical length of the input and output traces are 18.7 and 3.5 mm, respectively.

Fig. 20 shows the measurement setup of the proposed driver. The input pattern is a PRBS-31 with a single-ended amplitude of 300 mV_pp (at the chip inputs), generated from a Keysight M8195A arbitrary waveform generator. The LabMaster 10 Zi-A high-speed oscilloscope, along with its active probe, is used to measure the eye diagram of the output signal.

Fig. 21 shows the measured single-ended output eye diagrams at different data rates when either slice is enabled or both slices are simultaneously enabled and driven by identical input patterns. Clear open eyes are obtained up to 15 Gbps. The rise/fall times (20%–80%) at 15 Gbps are below 25 and 20 ps for slice I and slice II, respectively. The eye amplitude equals approximately 2 V for slice I and 1 V for slice II at different data rates. Hence, it could be deduced that the output modulation current is 80 and 40 mA, respectively. When both slices are enabled and driven with the same input pattern, the output current reaches 120 mA with an output eye amplitude of about 3 V.

At 15 Gbps, the eye width and height are 0.531 UI and 1.4 V for slice I, and 0.518 UI and 0.68 V for slice II. The random jitter ( ) and the deterministic jitter ( ) is about (0.014 and 0.376 UI) for slice I and (0.015 and 0.388 UI) for slice II. Consequently, the measured total jitter at a bit error rate of 10^–12 ( @ BER = 10^–12) equals 0.577 and 0.598 UI for slice I and slice II, respectively. When both slices are simultaneously enabled, , , and are 0.012, 0.354, and 0.526 UI, respectively. Meanwhile, the eye width and height are 0.533 UI and 2 V. Most of the jitter observed in the measurement results arises from the pattern generator, cables, connectors, PCB TLs, and oscilloscope. The fully differential input eye diagram, measured at the output terminals of the coupling capacitors, shows high jitter levels ( 0.03 UI, 0.297 UI, and 0.717 UI @ BER = 10^–12) as depicted in Fig. 22. Consequently, this input jitter severely degrades the output jitter performance of the driver at 15 Gbps.

Fig. 23 shows the output eye diagrams of the proposed driver when it is tested as a PAM4 transmitter at different data rates. In this test, the two slices are activated and a PRBS-31 pattern is applied to slice I (MSB path) while slice II (LSB path) is supplied with a one-bit delayed replica of the same pattern. The results demonstrate that the PAM4 eye diagrams still keep open and clear up to 30 Gbps (15 Gbaud/s) with a peak-to-peak amplitude of about 3 V (single-ended).

Table 2 summarizes the performance of the proposed driver, along with that of prior works. In our design, the modulation current is as high as 120 mA, with a power consumption of 1.228 W from a single –5.2 V supply. The proposed driver has a better FOM₁ than prior works that operate at nearby speeds. It also shows a high output power to power dissipation ratio that is defined using FOM₂. Ref. [4] has a slightly higher FOMs than the reported driver as it employs AC coupling to interface the output load, which helps to reduce the supply voltage, and hence the power consumption is also reduced. However, the AC coupling technique requires discrete off-chip coupling components, which causes signal distortion at high speeds and significantly degrades the driver gain at low frequencies^[19]. Ref. [11] also shows a higher FOM₁ than the proposed driver in NRZ mode. The reason is that Ref. [11] adopts the ABT technique which reduces the power dissipation on the expense of higher area. Also, the driver circuit in Ref. [11] is powered from three different supply voltages (1.2, 1.5, and 3.3 V), compared to a single supply in the reported driver. The reported modulation currents of the PAM4 driver in Ref. [21] and the NRZ driver in Ref. [30] are as low as 6.4 and 6.6 mA, respectively, making them only suitable for low current VCSEL diodes. As the modulation current decreases, the output voltage swing decreases, and consequently a lower supply voltage could be used. Therefore, the power consumption is significantly reduced as both of the total current and supply voltage are reduced, leading to a higher FOM₁. Moreover, smaller output transistors can be used, leading to higher speed operation. Therefore, it is unfair to directly compare FOM₁ of driver circuits with widely separated modulation currents. Nevertheless, the proposed NRZ/PAM4 driver has the highest modulation current with a better output power to power dissipation ratio (FOM₂), and it is still showing a comparable FOM₁ with these low current drivers. These results demonstrate the potential of the implemented driver to drive high current DFB lasers.

In this paper, the performance of a 0.15-µm GaAs pHEMT laser driver IC has been demonstrated. The driver supports both NRZ and PAM4 modulation schemes. A detailed design procedure was presented to optimize the driver circuit to achieve complete current switching at acceptable speed and power dissipation with a well-behaved transient response. The IC provides clear output eye diagrams at speeds up to 15 Gbps with NRZ and 30 Gbps (15 Gbaud/s) with PAM4 when driving 25-Ω loads. The reported driver demonstrates a high current driving capability along with better output power to power dissipation ratio, which makes it a good choice in driving high current DFB lasers.

The authors would like to acknowledge the support of the Chinese Academy of Science and The World Academy of Science (CAS-TWAS). In addition, they would like to thank the Information Science Laboratory Center of the University of Science and Technology of China for EDA tools. The work is partially carried out at the USTC Center for Micro and Nanoscale Research and Fabrication.