• Microelectronics
  • Vol. 53, Issue 2, 216 (2023)
CHEN Zhe1、2
Author Affiliations
  • 1[in Chinese]
  • 2[in Chinese]
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    DOI: 10.13911/j.cnki.1004-3365.220111 Cite this Article
    CHEN Zhe. A 4×112 Gbit/s PAM-4 Transimpedance Amplifier Based on 90 nm SiGe BiCMOS Process[J]. Microelectronics, 2023, 53(2): 216 Copy Citation Text show less
    References

    [1] IEEE Draft Standard for Ethernet Amendment 10: Media Access Control Parameters, Physical Layers and Management Parameters for 200 Gb/s and 400 Gb/s Operation: IEEE Std 802.3bs-2017 [S]. 2017.

    [2] LI M, CHEN Y, HU J, et al. A low noise 28 Gbaud/s linear PAM4 receiver front-end for optical communication applications in 0.13 μm BiCMOS technology [J]. Journal of Physics: Conference Series, 2021, 1815 (1): 012030.

    [3] HE A, GAI W X, YE B Y, et al. 56 Gb/s PAM4 receiver with an overshoot compensation scheme in 28 nm CMOS technology [J]. Microelectronics Journal, 2021, 116(10): 105236.1-105236.6.

    [4] SHI Y J, LI D, GAO S W, et al. A 112 Gb/s low-noise PAM-4 linear optical receiver in 28 nm CMOS [C] // International Conference on Electron Devices and Solid-State Circuits. Xi'an, China. 2019: 1-3.

    [5] LI Z H, TANG M Z, FAN T Y, et al. A 56-Gb/s PAM4 receiver analog front-end with fixed peaking frequency and bandwidth in 40-nm CMOS [J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2021, 68(9): 3058-3062.

    [6] LOPEZ I G, AWNY A, RITO P, et al. 100 Gb/s differential linear TIAs with less than 10 pA/√Hz in 130-nm SiGe:C BiCMOS [J]. IEEE Journal of Solid-State Circuits, 2018, 53(2): 458-469.

    [7] SACKINGER E. Analysis and design of transimpedance amplifiers for optical receivers [M]. New York: Wiley, 2018.

    [8] GILBERT B. A precise four-quadrant multiplier with subnanosecond response [J]. IEEE Journal of Solid-State Circuits, 1968, 3(4): 365-373.

    [9] WANG H, CHEN Y M, GAO Y, et al. A quad linear 56 Gbaud PAM4 transimpedance amplifier in 0.18 μm SiGe BiCMOS technology [C] // 32nd IEEE International System-on-Chip Conference. Singapore. 2019: 165-170.

    [10] LI H, BALAMURUGAN G, JAUSSI J, et al. A 112 Gb/s PAM4 linear TIA with 0.96 pJ/bit energy efficiency in 28 nm CMOS [C] // IEEE 44th European Solid State Circuits Conference. Dresden, Germany. 2018: 238-241.

    CHEN Zhe. A 4×112 Gbit/s PAM-4 Transimpedance Amplifier Based on 90 nm SiGe BiCMOS Process[J]. Microelectronics, 2023, 53(2): 216
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