[1] ALI A M A, DINC H, BHORASKAR P, et al. A 14 bit 1 GS/s RF sampling pipelined ADC with background calibration [J]. IEEE J Sol Sta Circ, 2014, 49(12): 2857-2867.
[2] WU J F, CHOU A, LI T W, et al. A 4 GS/s 13 b pipelined ADC with capacitor and amplifier sharing in 16 nm CMOS [C]// IEEE ISSCC. San Francisco, CA, USA. 2016: 466-467.
[3] ABOA M, GRAY P R. A 15-V, 10-bit, 143-MS/s CMOS pipeline analog-to-digital converter [J]. IEEE J Sol Sta Circ, 1999, 34(5): 599-606.
[4] BULT K, GEELENG J G M. A fast-settling CMOS opamp for SC circuits with 90-dB DC gain [J]. IEEE J Sol Sta Circ, 1990, 25(6): 1379-1384.
[5] DEVARAJAN S, SINGER L, KELLY D, et al. A 16-bit, 125 MS/s, 385 mW, 787 dB SNR CMOS pipeline ADC [J]. IEEE J Sol Sta Circ, 2009, 44(12): 3305-3313.
[6] ALI A M A, MORGAN A, DILLON C, et al. A 16-bit 250-MS/s IF sampling pipelined ADC with background calibration [J]. IEEE J Sol Sta Circ, 2010, 45(12): 2602 -2612.
[7] ZHENG X Q, WANG Z J, LI F L, et al. A 14-bit 250 MS/s IF sampling pipelined ADC in 180 nm CMOS process [J]. IEEE Trans Circ & Syst I: Regu Pap, 2016, 63(9): 1381- 1392.
[8] LEE C C, FLYNN M P. A SAR-assisted two-stage pipeline ADC [J]. IEEE J Sol Sta Circ, 2011, 46(4): 859-869.