Low noise ROIC integrated with correlated double sampling with adjustable intervals for hyperspectral applications

Shuang WU; Qing-Hua LIANG; Hong-Lei CHEN; Rui-Jun DING

doi:10.11972/j.issn.1001-9014.2024.02.017

Abstract

Low noise is a key requirement of readout integrated circuit (ROIC) in hyperspectral applications for its low radiation. Correlated double sampling (CDS) is commonly used to suppress noise. In this paper, CDS is improved by adjusting the time interval between the clamp and sample-and-hold (SH), which can filter low-frequency noise flexibly. A 640×512, 15 μm pixel pitch ROIC is designed and fabricated in 180 nm CMOS process. The input stage consists of low-noise capacitive trans-impedance amplifier (CTIA) and CDS with adjustable intervals (AICDS). A timing generator is proposed to extend the CDS reset time from 0 to 270 clock cycles. By extending the reset time to decrease the time interval, the noise electrons are significantly decreased from 39 e^- to 18.3 e^-. The SPECTRE simulation and the experimental results corroborate that the proposed structure AICDS can optimize noise performance of hyperspectral ROIC, thus can be widely used.

Keywords

adjustable interval capacitive trans-impedance amplifier （CTIA）correlated double sampling （CDS）hyperspectral imaging low noise readout integrated circuit （ROIC）

Introduction

Hyperspectral technologies have played a great role in vegetation monitoring，water resource management，geology and land cover^［1］. It acquires continuous，narrow-band image data with a high spectral resolution as shown in Fig. 1（a）. On one hand，it "captures" most of the subtle changes in the spectrum of a feature^［2］，which can be used to identify，classify，or quantitatively analyze substances. On the other hand，the light radiation dispersed and focused on hyperspectral infrared focal plane arrays （IRFPA），as presented in Fig. 1（b），is extremely low，resulting in high requirements for low noise. Table 1^［3-6］ shows the comparison of several hyperspectral sensors launched in recent years. The readout noise of readout integrated circuit （ROIC） is one of the key requirements for hyperspectral applications.

Instrument	CRISM	PRISMA	GF-5 AHSI	MAJIS	HyspIRI
Platform name	MRO	PRISMA	SAST3000	JUICE	HyspIRI
country	USA	Italy	China	Europe	USA
Launched year	2005	2018	2018	2022	2023
Spectral bands	-	249	330	-	220
Spectral range/µm	0.36~3.9	0.4~2.5	0.4~2.5	0.4~5.7	0.38~2.5
Spectral/nm	6.55	10	5~10	3~7	10
Format	640×480	1 000×256	512×512	1 024×1 024	-
detectors	HgCdTe	HgCdTe	HgCdTe	-	-
Pixel pitch/µm	27	30	30	15	-
ROIC input stage	CTIA	CTIA	CTIA	CTIA	-
Readout noise/e-	<100	<150/<350	60/275	<170	-

Table 1. Comparison of specifications of CRISM, PRISMA, Gaofen-5(GF-5), MAJIS and HyspIRI

View all Tables

Figure 1.Acquisition of hyperspectral data：（a） hyperspectral data cube；（b） schematic diagram of a hyperspectral imaging system

Different ROIC input stages are designed depending on the wavelength of infrared radiation. Capacitive trans-impedance amplifier （CTIA） can achieve high sensitivity，high linearity，and high injection efficiency^［7-8］. It’s commonly used for hyperspectral shortwave IRFPA ROIC input stage as shown in Table 1. However，its complex op-amp structure and reset switch not only occupy a large area，but also introduce thermal and KTC noise.

To suppress the low-frequency noise （1/f noise） and KTC noise，the correlated double sampling （CDS） has been widely studied in the field of IRFPA ROIC. The principle of CDS is to store 1/f noise on one clock phase and then subtract it from subsequent clock phases. The utilization of CDS in the column pitch or common output stage of IRFPA are reported in Refs. ［9-12］. In recent years，to pursue the objective of increasing the frame rate，the CDS is integrated in the pixel as presented in Refs. ［13-15］. As for the noise analysis，a method to evaluate the signal and noise of imagers with CTIA-CDS ROICs is developed by Jerris F. Johnson^［16］，and a cyclostationarity-based analytical model of charge amplification with CDS is proposed in Ref. ［17］. The analytical study of CDS KTC noise is presented in Refs. ［18-19］. These analyses provided designers with efficient solutions to noise assessment and ROIC optimization.

However，to enhance the CDS noise immunity，the influence of time interval between the clamp and sample-and-hold （SH） processes of CDS needs analysis and verification.

For this purpose，we first expound the noise mechanism of CDS with adjustable intervals （AICDS）. Then，the noise power spectral density （PSD） function of combined CTIA-CDS is calculated. Next，to verify the theory，a low-noise pixel circuit is designed，which integrates low-noise CTIA and AICDS controlled by a timing generator. In section 3，the circuit performance is simulated and the noise electron number is calculated. Finally，we draw conclusions.

1　Noise analysis

This section introduces the noise mechanism of CDS and combined CTIA-CDS as functions of time interval between the clamp and SH.

1.1　Noise mechanism of CDS

The proposed CDS circuit is depicted in Fig. 2（a），which consists of the sample capacitor $C_{0}$ ，reset switch $S_{2}$ ，sample-hold switch $S_{4}$ ，sample-hold capacitor $C_{s h}$ and its reset switch $S_{3}$ . The processed result is output to the column stage through the source-follower with a switch.

Figure 2.Correlated double sampling：（a） structure of CDS；（b） timing diagram of CDS，equivalent circuits：（c） reset of $C_{0}$ step at $t_{2}$ ；（d） reset of $C_{s h}$ and clamp step at $t_{3}$ ；（e） sample-hold step at $t_{4}$

Referring to the operating timing shown in Fig. 2（b），the equivalent circuits of different steps are shown in Figs. 2 （c），2（d），and 2（e）. The input signal is first sampled on $C_{0}$ . Secondly，when $S_{2}$ is off at $t_{2}$ ，the right plate of $C_{0}$ floats，clamping the charge stored in $C_{0}$ . Lastly，the redistribution of stored charge on $C_{0}$ and $C_{s h}$ achieves when $S_{4}$ turns on. As a consequence，the signals at different times are subtracted. The specific analysis of noise in a working cycle is as follows.

We consider $v_{n, i} (t)$ as the noise of time t，whose RMS is the square root of the sum of the independent noise powers. At the moment $t_{2}$ ，the noise charge stored on $C_{0}$ is：

Q_{n} = C_{0} ∙ v_{n, i} (t_{2})

.（1）

At the moment $t_{4}$ ，the noise voltage input to the left pole plate of $C_{0}$ becomes $v_{n} (t_{4})$ . According to the principle of charge conservation，the charges at the two moments correspond to：

C_{0} ∙ v_{n, i} (t_{2}) = C_{0} ∙ [v_{n, i} (t_{4}) - v_{n, o} (t)] - C_{s h} ∙ v_{n, o} (t)

.（2）

The output noise voltage is：

v_{n, o} (t) = \frac{C_{0}}{C_{0} + C_{s h}} [v_{n, i} (t_{4}) - v_{n, i} (t_{2})]

.（3）

Applying the Laplace transform to Eq.（3）：

v_{n, o} (s) = \frac{C_{0}}{C_{0} + C_{s h}} v_{n, i} (s) ∙ (1 - e^{- s T_{d}})

.（4）

Converting this to the frequency domain，the modulus of the transfer function is：

\begin{matrix} |H_{D} (ω)| = \frac{C_{0}}{C_{0} + C_{s h}} \sqrt[]{2 (1 - c o s ω T_{d})} \\ = 2 \frac{C_{0}}{C_{0} + C_{s h}} |s i n (ω T_{d} / 2)| \end{matrix}

.（5）

The red curve in Fig. 3（a） is the amplitude-frequency plot of the flicker noise，represented as：

Figure 3.1/f Noise Spectral Density reshaped by CDS with different $T_{d}$ ：（a） the spectral density of 1/f noise；（b） comparison of two CDS transfer functions with different $T_{d}$ ；（c） comparison of two output noise spectral density functions with different $T_{d}$

\bar{V_{n}} = \sqrt[]{\frac{K}{C_{o x} W L} ∙ \frac{1}{f}}

,（6）

where K is a quantity related to the manufacturing process， $C_{o x}$ is the gate-oxide capacitance per unit area and $W L$ is the channel area. Here，we assume $\sqrt[]{\frac{K}{C_{o x} W L}} = 1 n V$ to simplify calculations.

The transfer function of two different CDS is shown in Fig. 3（b），one is $s i n (ω T_{d} / 2)$ ，the other is $s i n (ω (2 T_{d}) / 2)$ . Here，we ignore the influence of capacitance and set $T_{d} = 0.5 μ s$ . The input noise is reshaped through CDS to the output noise presented in Fig. 3（c）. By reducing $T_{d}$ to lengthen the transfer function's period，it can be determined that the noise power in the low-frequency section may be decreased.

1.2　Output noise PSD of combined CTIA-CDS circuit

The subtraction step of CDS can be considered as a delay-subtractor ^［20］ as analyzed in the previous section. The CTIA，which is a switched-capacitor integrator，is equal to a first-order low-pass filter. The unit circuit structure model is shown in Fig. 4.

Figure 4.Structure of combined CTIA-CDS ROIC：（a） the schematic structure；（b） equivalent model structure

The noise power density of first-order low-pass filter：

S_{0} (ω) = \frac{S_{w}}{1 + {(ω τ_{0})}^{2}}

，（7）

where the time constant $τ_{0} = R C$ .

The noise power spectrum after the delayed subtractor is：

S_{D} (ω) = S_{0} (ω) {|H_{D} (ω)|}^{2}

.（8）

It can be seen from Eqs. （5） and （8） that reducing $T_{d}$ can decrease the noise power in the low-frequency section.

2　Proposed ROIC input stage

To verify the analysis above，a new ROIC input stage composed of low noise CTIA and AICDS is designed.

2.1　Combined CTIA-AICDS circuit

The combined CTIA-AICDS circuit proposed is shown in Fig. 5. The detector is directly connected to CTIA，which contains a reset switch $S_{1}$ and the feedback capacitor $C_{i n t}$ . Then，the AICDS receives the integral signal. Finally，the modified signal is transmitted through SF to the column stage.

Figure 5.Combined CTIA-AICDS ROIC

The conventional design uses a differential pair as the operational amplifier，where the MOS occupies nearly twice the area. Its input reference thermal noise voltage is ：

\bar{V_{n, i n}^{2}} = 8 k T (\frac{2}{3 g_{m 1}} + \frac{2 g_{m 3}}{3 g_{m 1}^{2}})

.（9）

This design uses a cascode type operational amplifier with an input reference thermal noise voltage of：

\bar{V_{n, i n}^{2}} = 4 k T (\frac{2}{3 g_{m 1}} + \frac{2 g_{m 3}}{3 g_{m 1}^{2}})

.（10）

It is close to half of the differential pair op-amp. This noise cannot be eliminated by the subsequent CDS structure ^［21］，but will be multiplied through two sampling process，having a large impact on the circuit noise performance. Therefore，the cascode op-amp has benefits on noise reduction and area saving.

Considering to further reduce the noise of CTIA，the following guidelines must be adhered to in the design.

The operating current $I_{D}$ of the cascode must be low. The small operating current ensures a smaller power consumption，reducing the detector image interference caused by the heat of the pixel circuit. $I_{D}$ is determined by V_bias，which is provided through the current mirror in the bias circuit. The current mirror of the selectable channel generates $I_{D}$ around 100 $n A$ in this application.

$\frac{W}{L}$ of input transistor $M_{1}$ must be large whereas $\frac{W}{L}$ of load transistor $M_{3}$ must be small.

These two conditions make M₁ work in the sub-threshold region，where the leakage current of M₁ is：

I_{D} = I_{0} e x p \frac{V_{G S}}{ζ V_{T}}

，（11）

where ζ > 1 is a non-ideal factor and $V_{T} = k T / q$ .

At this point， $I_{D}$ is exponentially related to $V_{G S}$ and the trans-conductance of MOS device M₁ is：

g_{m 1} = \frac{d I_{D}}{d V_{G S}} = \frac{1}{ζ V_{T}} I_{D}

.（12）

The gain of the operational amplifier is

A_{V} = - g_{m 1} \{[(1 + g_{m 2} r_{o 2}) r_{o 1} + r_{o 2}] ‖ r_{o 3}\}

.（13）

It guarantees a large gain of M₁ in the subthreshold region as we can conclude from Eqs. （12） and （13）.

The operating timing of the pixel circuit is shown in Fig. 6. Adjusting the additional CDS reset time $T_{r}$ can regulate $T_{d}$ . At the beginning of each frame， $S_{1}$ and $S_{2}$ turn on to reset $C_{i n t}$ and $C_{0}$ . After enough reset time， $S_{1}$ is disconnected to start the integration process. Due to the voltage regulation characteristic of the op-amp， $V_{i n}$ remains unchanged and $V_{0}$ is integrated as photocurrent is injected into the feedback capacitor. Subsequently，the transmission to CDS of $V_{0}$ operates as described in section 2.

Figure 6.Timing diagram and node voltage of the proposed ROIC pixel

2.2　Timing generator of AICDS

The proposed timing generator can adjust the additional CDS reset time $T_{r}$ relative to integration-reset time $t_{1}$ as exhibited in Fig. 6. The CTIA integral reset signal $i n t r s t$ generates two pulse signals $φ_{0}$ and $φ_{1}$ to mark its rising and falling edges. As seen in Fig. 7，the division，counter，comparator，and latch make up the CDS timing control mechanism. It operates as follows.

Figure 7.The proposed timing generator of AICDS

a. The high-frequency master clock CLK is first divided into a clock，whose cycle period is determined by the required minimum time step.

b. The counter generates 4 bits Gray-code from the divided clock.

c. Comparing Gray-codes with control bits $T R [3 : 0]$ ，it generates a pulse signal $φ_{c}$ to determine the falling edge of $T_{r}$ when digital bits equal.

d. $φ_{1}$ and $φ_{c}$ determine the operational time of the counter.

e. $φ_{0}$ and $φ_{c}$ are injected to the latch to generate $c d s r s t$ .

A time regulation step of 18 clock cycles is achieved by dividing the frequency with 9 DFFs. With 4 digital bits，a CDS reset time regulation ranging from 0 μs to 27 μs can be achieved for the master frequency CLK of 10 MHz，as shown in Table 2.

$T R [3 : 0]$	Clock cycles
$0000$	$0$
$0001$	$18$
$0010$	$36$
$\dots$	$\dots$
$1111$	$270$

Table 2. CDS reset time regulation

View all Tables

3　Circuit performance and noise simulation

In order to confirm the performance of circuit design，we have simulated the schematic using SPECTRE of Cadence. This circuit is designed in standard 180 nm CMOS process with 3.3 V supply voltage. Integral capacitance $C_{i n t} = 4 f F$ ，CDS sample capacitor $C_{0} = 200 f F$ and SH capacitor $C_{S H} = 20 f F$ .

3.1　Circuit performance simulation

The performance of CTIA amplifier is simulated and shown in Table 3. Sweeping the injection photocurrent from 200 pA to 900 pA，the output waveform of $V_{0}$ and $V_{2}$ is presented in Fig. 8.

Amplifier parameter
gain	59.6 dB
Phase margin/°	60
Bandwidth/Hz	8M
Swing/V	2.23（1-3.23）
pixel pitch/μm	15
DC current/nA	68~100

Table 3. The performance of CTIA amplifier

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Figure 8.Integration and dynamic simulation

Figure 9 shows the simulation results for the CDS reset time regulation. Setting $T C D S R S T [3 : 0] = 1001$ ，the simulation waveforms demonstrate that $T_{r}$ is 9 $μ s$ ，which is consistent with intended specification.

Figure 9.Time sequence transient simulation

3.2　Noise simulation

The common simulation method is to sum the noise of each separate cell. Since the CTIA reset noise and CDS of this circuit are correlated，the traditional simulation method cannot accurately reflect the impact of the interval on the noise. This design adopts transient noise simulation，which can accurately reflect the noise magnitude during the hold phase.

We evaluate the equivalent noise charge （ENC） of input node to verify the noise performance of AICDS. The ENC $μ_{n}$ is described as follows：

μ_{n} = \frac{V_{n}}{e G}

，（14）

where $V_{n}$ is the noise voltage of output node and electron charge $e = 1.6 \times 10^{- 19} C$ . The conversion gain $G$ is presented as：

G = \frac{V_{2}}{μ_{e}}

，（15）

where $V_{2}$ is the output voltage and $μ_{e}$ is the electrons injected into the ROIC.

In this design， $μ_{e}$ is integrated from $t_{2}$ to $t_{4}$ as shown in Fig. 6.

μ_{e} = I_{d e t} T_{d} = I_{d e t} (T_{i n t} - T_{r})

，（16）

where $T_{i n t} = 34 μ s$ .

As for $V_{2}$ ，we can calculate it from Eq. （3）.

V_{2} = \frac{C_{0}}{C_{0} + C_{s h}} \frac{I_{d e t} T_{d}}{C_{i n t}}

.（17）

Then the conversion gain G is：

G = \frac{C_{0}}{C_{0} + C_{s h}} ∙ \frac{1}{C_{i n t}}

.（18）

For the case of $C_{d e t} = 40 f F$ and photocurrent $I_{d e t} = 20 p A$ ，24999 transient noise simulations are performed and sampled.

For the results，the histogram of output voltage $V_{2}$ under different settings of $T_{r}$ is shown in Fig. 10. The results are finally brought into Eq. （14） to calculate the number of noise electrons.

Figure 10.The histogram of $V_{2}$ under different settings of $T_{r}$

Noise electrons under different settings of $T_{r}$ are shown in Fig. 11. The noise electron number of readout circuit ranges from 48.72 to 22.15，with $T_{r}$ varying from 1 $μ s$ to 11 $μ s$ . After $T_{r} = 11 μ s$ ，the noise is stable at about 22 $e^{-}$ which is mainly decided by the post-stages.

Figure 11.ENC and SNR vary with $T_{r}$

As $T_{r}$ increases，the SNR can reach 42.98 $d B$ at $T_{r} = 8 μ s$ . However，after that，the signal quantity declines with decreased $T_{d}$ whereas the noise stays constant，resulting in attenuation of SNR. The simulation results show that extending $T_{r}$ ，in other words，decreasing $T_{d}$ ，can suppress the noise of combined CTIA-CDS ROIC.

4　Experimental results

The full system is designed and fabricated in TSMC 0.18 μm CMOS technology. The fabricated chip is shown in Fig. 12，annotated with the floorplan. It consists of 640×512 array of 15 μm×15 μm pixel area. To meet the requirement of low noise，the pixel array is located at the center of the chip，while separated analog and digital blocks are placed at the edge.

Figure 12.Layout and floorplan of the fabricated chip

The platform designed to test the system is shown in Fig. 13^［22］. LVDS module can generate the working time sequence and collect the output signal produced by the chip. The LabView-based test platform can control voltage，clock，and waveform. In addition，the acquired readout signal of the pixel array can be displayed as a grayscale map.

Figure 13.Schematic diagram of experimental platform

To compare the noise performance of input stage with and without CDS，we designed a test schematic to turn off the CDS function as shown in Fig.14 （a）. The timing diagram is presented in Fig.14 （b），where we can see $S_{2}$ is invariably off，while $S_{5}$ closes to be constantly controlled by a digital bit. As shown in Figs. 15（a） and 15（b），we get the grayscale map over 640×512 pixel array with CDS off and on. Intuitively，the uniformity with CDS on is far better than that with CDS off，which demonstrates that the noise can be suppressed by CDS. A closer look can be taken by acquiring partial 16×16 array to check the noise distribution，which is shown in Figs.15 （c） and 15（d）. The noise with CDS on is far lower and much flatter than that with CDS off.

Figure 14.Structure of CDS test：（a） the schematic structure；（b） timing diagram

Figure 15.The output voltage acquisition：（a） the grayscale map over 640×512 array when CDS-off；（b） the grayscale map over 640×512 array when CDS-on，the output noise acquisition；（c） the histogram of 16×16 segment when CDS-off；（d） the histogram of 16×16 segment when CDS-on

The clock frequency is set at 500 kHz，which means the adjustment step is $36 μ s$ . The additional CDS reset time $T_{r}$ is adjusted and settled in condition of $T_{i n t} = 360 μ s$ and $T_{i n t} = 640 μ s$ . We measure the influence of $T_{r}$ on the noise through the ratio of $γ = T_{r} / T_{i n t}$ as presented in Fig. 16，where we can conclude that：

Figure 16.The output noise voltage in condition of （a） CDS off and （b） varying ratio $γ$ when CDS turns on

a. The noise electron is up to 18.3 $e^{-}$ optimally by adjusting $T_{r}$ ，while the noise number is 39 in the case of turning off CDS. It shows an attenuation of 52%；

b. With CDS on，the noise has a tendency of decreasing with the increment of $T_{r}$ ，whose slope is -24 µV.

5　Conclusion

In this paper，CDS with adjustable intervals has been proposed as a new technology to improve the noise performance of ROIC. It has been analyzed that decreasing the time interval between the clamp and SH can reduce the pre-stage noise. The feasibility of the technique is proved in a combined CTIA-AICDS controlled by a timing generator in 180 $n m$ CMOS process. 24999 transient noise simulations demonstrate that by adjusting the interval，the ENC of input stage attenuates by 54%，and SNR is enhanced by 5 $d B$ . The experimental test results verify that the proposed structure can suppress the noise by 52% than CDS off and reduce the noise with a slope of -24 µV. It can be broadly used in Hyperspectral applications of low background radiation.

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