• Microelectronics
  • Vol. 51, Issue 2, 188 (2021)
DENG Chengda, LUO Ping, TANG Tianyuan, and WANG Qiang
Author Affiliations
  • [in Chinese]
  • show less
    DOI: 10.13911/j.cnki.1004-3365.200248 Cite this Article
    DENG Chengda, LUO Ping, TANG Tianyuan, WANG Qiang. A Dynamic Regulation Leading Edge Blanking Circuit[J]. Microelectronics, 2021, 51(2): 188 Copy Citation Text show less

    Abstract

    Based on topological structure of primary side feedback flyback converter, a dynamic regulation leading edge blanking circuit suitable for PWM、PFM regulation mode was proposed. First, when the system was working in PWM or PFM mode, the output current information and the system operating frequency were detected respectively to generate the dynamically regulated front blanking signal, which avoiding the miss-sampling of knee voltage caused by high frequency oscillation of the auxiliary winding. Secondly, the front blanking time was dynamically adjusted to reduce the power consumption of the lap sampling circuit in the full load range. The designed sampling circuit could obtain the output current information and the working frequency information of the system, which avoiding the miss-sampling of the knee voltage caused by the nonlinear adjustment of the blanking time when working conditions of the flyback converter were changed. The circuit was designed in a 0.18 μm BCD process. The simulation results showed that the minimum error of dynamic regulation leading edge blanking time was 4%.
    DENG Chengda, LUO Ping, TANG Tianyuan, WANG Qiang. A Dynamic Regulation Leading Edge Blanking Circuit[J]. Microelectronics, 2021, 51(2): 188
    Download Citation