[1] HINOJO J M, MARTNEZ C L, TORRALBA A. Internally compensated LDO regulators for modern system-on-chip design [M]. Berlin: Springer Int Publishing AG, 2018: 10-15.
[2] HENG S, PHAM C K. A low-power high-PSRR low- dropout regulator with bulk-gate controlled circuit [J]. IEEE Trans Circ Syst II: Expr Brie, 2010, 57(4): 245-249.
[3] MING X, LI Q, ZHOU Z, et al. An ultrafast adaptively biased capacitorless LDO with dynamic charging control [J]. IEEE Trans Circ Syst II: Expr Brie, 2012, 59(1): 40-44.
[4] MANNAMA V, SABOLOTNY R, STRIK V. Ultra low noise low power LDO design [C]// Proceed Int Biennial Baltic Elec Conf. Tallinn, Estonia. 2006: 1-4.
[5] HOON S K, CHEN S, MALOBERTI F, et al. A low noise, high power supply rejection low dropout regulator for wireless system-on-chip applications [C]// Proceed IEEE Custom Integr Circ Conf. San Jose, CA, USA. 2005: 759-762.
[6] WONG K, EVANS D. A 150 mA low noise, high PSRR low-dropout linear regulator in 0.13 μm technology for RF SoC applications [C]// Proceed 32nd European Sol Sta Circ Conf. Montreaux, Switzerland. 2006: 532-535.
[7] GUO J, LEUNG K N. A fold-back current-limit circuit with load-insensitive quiescent current for CMOS low dropout regulator [C]// IEEE Int Symp Circ Syst. Taipei, China.2009: 2417-2420.
[8] LIN C, FENG Q. Design of current limiting circuit in low dropout linear voltage regulator [C]// Asia-Pacific Microw Conf Proceed. Suzhou, China. 2005.