[1] Liu Y H, Heuvel J H C, Kuramochi T, et al. An ultra-low power 1.7~2.7GHz fractional-N sub-sampling digital frequency synthesizer and modulator for IoT applications in 40nm CMOS[J]. IEEE Trans. on Circuits and Systems, 2017, 64(5): 1094-1105.

[2] Wang B, Liu Y H, Harpe P, et al. A digital to time converter with fully digital calibration scheme for ultra-low power ADPLL in 40nm CMOS[C]// Proc. IEEE Inter. Symp. on Circuits and Systems (ISCAS), 2015: 24-27.

[3] Zhuang J, Staszewski R B. A low-power all-digital PLL architecture based on phase prediction[C]// Proc. of 19th IEEE Inter. Conf. on Electronics, Circuits and Systems (ICECS), 2012: 797-800.

[4] Temporiti E, Weltin-Wu C, Baldi D, et al. A 3.5GHz wideband ADPLL with fractional spur suppression through TDC dithering and feedforward compensation[J]. IEEE J. of Solid-State Circuits, 2010, 45(12): 2723-2736.

[5] Park M, Perrott M H, Staszewski R B. An amplitude resolution improvement of an RF-DAC employing pulsewidth modulation[J]. IEEE Trans. on Circuits and Systems Ⅰ: Regular Papers, 2011, 58(11): 2590-2603.

[6] Kim W, Park J, Kim J, et al. A 0.032mm2 3.1mW synthesized pixel clock generator with 30psrms integrated jitter and 10~630MHz DCO tuning range[C]// ISSCC Dig. Tech. Papers, 2013: 250-251.