• Journal of Electronic Science and Technology
  • Vol. 23, Issue 2, 100306 (2025)
Mahamudul Hassan Fuad1,2,*, Md Faysal Nayan2, Sheikh Shahrier Noor2, Rahbaar Yeassin2, and Russel Reza Mahmud2,*
Author Affiliations
  • 1Department of Electrical and Electronic Engineering, Dhaka International University, Dhaka, 1212, Bangladesh
  • 2Department of Electrical and Electronic Engineering, Ahsanullah University of Science and Technology, Dhaka, 1208, Bangladesh
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    DOI: 10.1016/j.jnlest.2025.100306 Cite this Article
    Mahamudul Hassan Fuad, Md Faysal Nayan, Sheikh Shahrier Noor, Rahbaar Yeassin, Russel Reza Mahmud. Comprehensive performance analysis of CMOS and CNTFET based 8T SRAM cell[J]. Journal of Electronic Science and Technology, 2025, 23(2): 100306 Copy Citation Text show less

    Abstract

    In recent years, carbon nanotube field effect transistor (CNTFET) has become an attractive alternative to silicon for designing high-performance, highly stable, and low-power static random access memory (SRAM). SRAM serves as a cache memory in computers and many portable devices. Carbon nanotubes (CNTs), because of their exceptional transport capabilities, outstanding thermal conductivities, and impressive current handling capacities, have demonstrated great potential as an alternative device to the standard complementary metal-oxide-semiconductor (CMOS). The SRAM cell design using CNTFET is being compared to SRAM cell designs built using traditional CMOS technology. This paper presents the comprehensive analysis of CMOS & CNTFET based 8T SRAM cell design. Because of the nanoscale size, ballistic transport, and higher carrier mobility of the semiconducting nanotubes in CNTFET, it is integrated into the 8T SRAM cell. The approach incorporates several nonidealities, including the presence of quantum confinement consequences in the peripheral and transverse prescriptions, acoustic and transparent photon diffraction in the region surrounding the channel, as well as the screening effects by parallel CNTs in CNTFETs with multiple CNTs. By incorporating Stanford University CNTFET model in CADENCE (virtuoso) 32 nm simulation, we have found that CNTFET SRAM cell is 4 times faster in terms of write/read delay and the write/read power delay product (PDP) value is almost 5 times lower compared to CMOS based SRAM. We have also analyzed the effect of temperature & different tube positions of CNTs on the performance evaluation of the 8T SRAM cell.

    1 Introduction

    The limits of metal oxide semiconductor (MOS)-like architectures become apparent when feature size decreases due to technological advancements. The static random access memory (SRAM) module occupies the majority of the chip space within central processing unit (CPU). As device architecture continues to get smaller and smaller, the quantum mechanical impact becomes more significant [1,2]. In addition to tunneling, the quantum confinement effect has a significant impact on carbon nanotube field effect transistor (CNTFET) device functionality [3,4]. Quantum confinement occurs as the parameters of the carbon nanotubes (CNTs) approximate the wavelength of de Broglie’s charge carriers, resulting in quantized energy levels. This influences carrier mobility and threshold voltage in CNTFETs. Employing optimal CNT diameters and maintaining consistency throughout production might alleviate these discrepancies. Furthermore, choosing the correct chirality for CNTs can provide uniform electrical characteristics. Bandgap can be represented as $ {E}_{g}=\dfrac{2 \hbar {V}_{F}}{d} $, where Eg is the bandgap, VF is the Fermi velocity, $ \hbar $ is the reduced Planck’s constant, and d is the CNT diameter. The healthcare industry’s growing appetite for Internet of things (IoT)-based infrastructure has paved the way for new ways to connect humans and computers. Because of its role in storing data at fast speeds, static SRAM is a crucial component of embedded IoT device [5]. SRAM, as the mainstay of the very large scale integration (VLSI) industry, plays a crucial role. Particularly, embedded SRAM comprises an important portion of system-on-chip area [6]. It is a crucial component in adaptable microprocessor-based systems with an extensive variety of applications, such as intelligent smartphones and watches, satellite technology, defense-related wireless networked sensors, mobile and battery-powered devices, flexible electronics, and IoT [7,8]. In this fields, the requirement for on-chip SRAMs with low power consumption and extended battery life is important. The International Technology Roadmap for Semiconductors (ITRS) highlights that 90% of chip area is occupied by SRAM [9]. Moreover, SRAMs have a substantial effect on the overall system performance [10], making them indispensable for high-performance processors that demand synchronization with the quickest memory options [11,12]. By providing improved performance in nanoscale domains, reduced power consumption, and increased speed, CNTFETs can circumvent the scaling constraints of traditional complementary metal-oxide-semiconductors (CMOS). SRAM cells, which are essential in many high-demand applications like mobile devices, IoT, and systems powered by artificial intelligence (AI), benefit greatly from these characteristics. In comparison to traditional CMOS SRAM cells, which need a higher voltage for stable operation, CNTFET based SRAM cells display much decreased static and dynamic power dissipation because of their capability to function at lower supply voltages. When it comes to high-performance computing (HPC) systems, where power and thermal control are paramount, this low-power feature is invaluable. Compared to silicon-based CMOS, CNTFET based SRAM cells offer a greater electron mobility of around 10 000 cm²/(V·s), leading to quicker switching times and smaller access delay. With their increased mobility, CNTFET based SRAM cells are perfect for high-density memory designs in HPC systems, since they allow for smaller transistors without sacrificing performance. In order to prolong the life of their batteries, mobile devices require memory solutions that reduce energy usage. SRAM cells based on CNTFETs are more energy efficient than other types because they can run on lower supply voltages without sacrificing read/write stability. In mobile settings, when battery capacity limits the power envelope, power reduction is critical. The enhanced carrier transport capabilities of CNTs allow CNTFET based SRAM cells to provide faster switching rates and shorter read/write access times. When it comes to mobile devices, this is of utmost importance since the user experience is greatly improved by quick data retrieval for tasks like gaming, multimedia processing, and AI-driven apps (like voice recognition) [13]. As the channel length diminishes over time, CMOS-based devices encounter short channel effects, including subthreshold swings, drain-induced barrier lowering, and diminished gate control. These effects will impact the device performance at the nanoscale and diminish the overall efficacy of the device. Conversely, CNTFETs provide enhanced electrostatic control, facilitating improved scalability. Owing to their one-dimensional architecture and ballistic transport properties, CNTFETs may function well at diminished channel lengths, alleviating short-channel effects and facilitating additional miniaturization without considerable performance degradation. Leakage currents, especially in the off-state, provide a significant challenge for CMOS-based SRAM as device dimensions decrease. This results in heightened static power dissipation, which is unfavorable for low-power applications. CNTFET based SRAM cells, characterized by a high intrinsic on-off current ratio and reduced leakage, present an appealing alternative by substantially decreasing static power consumption, hence enhancing their suitability for energy-efficient designs.

    SRAM is an essential component in current electronic systems because of its fast operation and low energy usage. With the rising need for smaller and more efficient devices, it is crucial to reduce the size of SRAM technology. Conventional CMOS technology has been the fundamental basis for SRAM design. However, when the size of devices decreases to nanoscale levels, CMOS encounters substantial difficulties. These factors encompass heightened leakage currents, variability concerns, and rising power consumption, all of which pose a threat to the performance and dependability of upcoming SRAM cells. CNTFETs have recently gained attention as a viable substitute for traditional CMOS technology in this particular scenario. CNTFETs have enhanced electrostatic regulation, diminished leakage currents, and decreased power dissipation, rendering them very appropriate for nanoscale applications. CNTs possess distinctive characteristics, including elevated carrier mobility and exceptional thermal conductivity, which greatly augment the capabilities of CNTFETs in addressing the constraints of CMOS technology, namely in the development of memory cells. Consequently, several academic and industry research groups have undertaken efforts to integrate novel semiconductors as the channel material. Nevertheless, there is a preference for hybrid technology that utilizes silicon as the substrate for fabrication processes, heat transmission, and mechanical support. An example of such a system is the CNTFET, which is built on CNTs [14]. The CNTFETs show promise due to their distinctive one-dimensional band structure, which inhibits backscattering and enables near ballistic operation [15]. Additionally, CNTFET exhibits a much reduced off current, resulting in a considerable decrease in power consumption when the CNTFET is in the off state [16]. Although there has been much study conducted on SRAM cell designs, the investigation of 8T SRAM cells utilizing a hybrid technique that integrates both CNTFET and CMOS technology is still limited. Prior research has mostly concentrated on either CNTFET or CMOS-based technologies, resulting in a lack of comprehension of the combined advantages that hybrid architecture may provide. The existence of this gap provides a notable opportunity to explore how the combination of CNTFETs with CMOS technology might enhance the efficiency, dependability, and expandability of SRAM cells. Several designs of SRAM cells based on CNTFET have been presented in recent literature [1618]. The suggested designs anticipate enhanced performance of SRAM based on CNTFET compared to its CMOS equivalent in terms of static noise margin, standby power, access time, and write margin. A low leakage SRAM cell employing a CNTFET and forced stack approach was proposed [19]. CNTFETs encounter difficulties in memory integrated circuits and digital integrated circuits related to scaling feature sizes, heightened leakage currents, and diminished dependability. Challenges with internal and inter-chip interconnects in memory chips utilizing conventional binary logic have emerged as significant in binary circuitry. Future research should concentrate on the utilization of CNTFET circuits in multi-valued logic and non-volatile memory to address the increasing need for computation and storage [20].

    A significant challenge in CNTFET production is attaining accurate alignment and positioning of CNTs on a broad scale. CNTs exhibit a tendency for combining, making it challenging to maintain regular spacing and orientation during deposition, hence affecting device consistency and dependability [21]. Contemporary CNT production techniques frequently yield a combination of metallic and semiconducting CNTs. Separating semiconducting CNTs from metallic CNTs is crucial for the effective operation of CNTFETs [22]. This separation is difficult and not yet economically viable on an industrial scale. CNTFETs must be incorporated into current CMOS technologies for hybrid circuits. The elevated temperature prerequisites for CNT growth and deposition may compromise conventional CMOS materials, resulting in compatibility challenges. Moreover, it is essential that CNTFETs may be produced utilizing normal CMOS process flows with minimal modifications to provide scalability [23]. CNTFET technology is mostly concentrated on the deployment of SRAM. With technological advancement, it is imperative to expand CNTFET technology to other memory architectures. The implementation of CNTFET in SRAM offers several benefits, including reduced power consumption and enhanced performance; however, various memory types present unique challenges and needs regarding architecture and operation. Utilizing CNTFET technology in alternative memory architectures can boost memory performance and drive the overall progress of memory technology. The transition of CNTFET technology from SRAM to alternative memory architectures is a promising research direction [24].

    The aim of this study is to create and assess an 8T SRAM cell that combines CNTFET and CMOS technologies. The study utilizes extensive simulations to examine crucial performance indicators, such as velocity, energy use, and robustness, and contrasts them with conventional CMOS based SRAM architectures. This work seeks to enhance the comprehension of hybrid memory technologies and aid in the creation of more effective and scalable nanoscale memory solutions by connecting CNTFET and CMOS research in the SRAM cell design. This study has important ramifications for the future of memory technology, since it presents a means to get improved performance and reduced power usage in SRAM cells. The results of this study might have a significant impact on advancing the development of memory technology, facilitating the continual progress of high-performance and energy-efficient electronic devices. Future research will assess the effects of various CNTFET parameters, including diameter, dielectric material, and oxide thickness, leading to an improved selection of CNTFET based SRAM designs.

    2 Schematic and layout verification of 8T SRAM cell

    Figs. 1 and 2 show the schematic diagram and the output curve of CNTFET based 8T SRAM cell. Here, SRAM is comprised of eight CNTFET-based transistors, while the circuit is comprised of two P-type CNTFET (PCNTFET) and six N-type CNTFET (NCNTFET). In Fig. 2, BL represents the bit line where the input data is provided, BLB is the opposite bit of BL, WWL represents the controls for the write data transistors, RWL represents the enable read port, ROUT is the read output data, pwr represents the total power consumption of the circuit, PM represents the P-type transistor, and NM represents the N-type transistor. In Fig. 3, VSS represents the grounding or reference node in the layout, QBAR represents the inverse output bit of the SRAM, Q represents the output bit of the SRAM, and VDD represents the DC power supply of the circuit.

    Schematic of 8T SRAM cell.

    Figure 1.Schematic of 8T SRAM cell.

    Output wave form of CNTFET based 8T SRAM cell.

    Figure 2.Output wave form of CNTFET based 8T SRAM cell.

    Layout design CNTFET based of 8T SRAM cell.

    Figure 3.Layout design CNTFET based of 8T SRAM cell.

    The stimuli simulation timings for those ports are given in Table 1. The curve in Fig. 2 is generated using the corresponding data shown in Table 1. Fig. 3 shows the layout of 8T SRAM cells with deign rule check (DRC) and layout versus schematic (LVS) verification, indicating that there is no mismatch between schematic and layout design of this SRAM.

    Stimuli (Setup)
    ParameterRBLRWLWWLBLBLBVDD (DC)
    Voltage 10 V0 V0 V0 V1 V1 V
    Voltage 21 V1 V1 V1 V0 V
    Period30 ns40 ns30 ns60 ns60 ns
    Delay time10 ps10 ps10 ps10 ps10 ps
    Rise time10 ps10 ps10 ps10 ps10 ps
    Fall time10 ps10 ps10 ps10 ps10 ps
    Pulse width15 ns20 ns25 ns30 ns30 ns

    Table 1. Device parameter.

    2.1 Write operation

    During the write operation of an 8T SRAM cell, the stored data is given to BL, and the reverse data is given to the BLB port. Two access transistors, designated NM2 and NM3, are available for the transfer of data. The WWL bit line controls the operation of these access transistors. When the value of WWL is altered from 0 to 1, the NCNTFET transistor became operational. BL data was sent to storage node Q, and BLB data was sent to storage node QBAR. Two inverters are cross-coupled in this 8T SRAM cell. When the data in the Q node is 0 and the data in the QBAR node is 1, this cross-coupled condition will trigger the transistors PM1 and NM0. Therefore, the Q terminal will be hooked up to the ground, and the QBAR terminal will be connected to VDD. This will produce a powerful 0 at the Q position and a strong 1 at the QBAR point [25].

    2.2 Read operation

    For read operation stability, the 8T CNTFET based SRAM has two additional transistors connected compared with the 6T CNTFET based SRAM. These transistors are interconnected in sequence. The gate terminal of the NM4 transistor is controlled by RWL, whereas the drain is coupled to RBL. The gate terminal of the transistor NM5 is controlled by the data storage node QBAR. During a read operation employing the ROUT port, the read result can be obtained. When the values of BL and its reverse BLB are transferred to the storage nodes Q and QBAR, respectively, we access the data through the read operation. To complete the read operation, we need to set RBL and RWL to high values, which will turn on the NM4 transistor. When the value of storage node Q is 0 and the value of storage node QBAR is 1, the condition is met. This will turn on the transistor NM5 and connect the read signal port ROUT to the ground. As a result, we can read the data of storage node Q, which is 0, with ease. When the value of storage node Q is 1 and the value of storage node QBAR is 0, the condition is met. It will result in turning off the transistor NM5 and connecting the read signal port ROUT to the recharging point VDD. Consequently, we can easily read the information from the storage node Q easily, which is 1.

    2.3 Hold operation

    WWL is kept low during the duration of the hold process. NM2 and NM3 access transistors are turned off, so that Q and QBAR nodes that store data are isolated from BL and may faithfully restore their prior states. The bit is stored in a cross-coupled inverter with four transistors during the hold operation.

    3 Result and discussion

    3.1 Device parameter definition and default values for logic gate simulation

    The input parameters for both CNTFET and CMOS based 8T SRAM cell are shown in Table 1. Here, the supply voltage used 1 V, and the delay, rise time, and fall time of the data at each port are set to 10 ps. According to the setup detailed in Table 1, the output is shown in Fig. 2. The device parameters of CNTFET in the simulation environment are shown in Table 2.

    Specifications of deviceDetailed explanation of the parametersDefault value
    LchChannel length in physical terms. Additional quantum mechanical consequences need to be considered for channel lengths below 10 nm, when this reasoning may not hold.32.0 nm
    LgeffThe (intrinsic) channel region has a mean uncontrolled path due to non-ideal flexible dispersion.200.0 nm
    LssThe length of the source side development section (CNT) that was intentionally doped.32.0 nm
    LddThe distance between the doped CNT source region and the drain-side expansion zone.32.0 nm
    EfiFermi level within an altered source/drain tube.0.6 eV
    KgateDielectric permittivity.16.0
    ToxOxide thickness at the top gate (planer gate).4.0 nm
    CsubThe capacitance of interaction among the channel region along with the substrate (back gate).20.0 pF/m
    CcsdThe capacitance of association within the channel’s interior region and source-drain region.0.0 pF/m
    Couple ratioCoupling capacitance between the channel and discharge, represented as a share of Ccsd.0.0

    Table 2. Device parameter definitions and default values [26,27].

    In these simulations we have considered the ballistics transport of CNTFETs. In CNTFETs, charge carriers traverse the channel with low dispersion due to the narrow channel lengths, resulting in near-ballistic transport. This markedly enhances both the on-state current and the switching speed of the device. Maintaining superior CNT development and reducing flaws in the channel helps maintain ballistic transport features, hence increasing the overall speed of the SRAM cells. The free flow of charge carriers over relatively long distances in the material is a phenomenon usually observed in quasi-one-dimensional (1D) structure like CNTs. If:

    Lλ, then it is non-ballistic transport;

    Lλ, then it is ballistic transport.

    where L represents the channel length and λ represents the electron mean free path.

    3.2 Parametric analysis of CMOS based conventional 8T SRAM cell

    This section provides an in-depth investigation of the effectiveness of an 8T SRAM cell under different temperature circumstances. This study examines the effect of temperature variances on important performance indices, including read and write delays and power consumption. At higher temperatures, the performance of a transistor is influenced by a reduction in mobility, a shrink in threshold voltage, and an increase in intrinsic free carriers [28].

    Write delay is the duration needed to store data into an SRAM cell once the write process has been started. With rising temperature, the movement of charge carriers in CMOS transistors diminishes, resulting in a decrease in the strength of the current driving capability. This leads to a decreased rate of charging or discharging of the internal node capacitances, which directly affects the speed at which the SRAM cell may be written. Lower temperatures result in increased electron and hole mobility, resulting in quicker switching times and reduced write delays [29]. Nevertheless, when the temperature increases, the decline in mobility leads to a rise in write latency. In addition, elevated temperatures can worsen the leakage currents in the transistors, which can have a further impact on the write operation. Read delay refers to the duration required to retrieve stored data from an SRAM cell following the initiation of a read operation. The read delay, like the write delay, is affected by the mobility of charge carriers in the transistors. Increased temperatures result in decreased mobility, causing a slower response from the bit lines and sense amplifiers, ultimately leading to longer read delays. In addition, higher temperatures can make the SRAM cell more vulnerable to noise and bit-flips, which may need longer sensing periods to precisely discern the stored data, thus causing further delays in reading. Lower temperatures provide quicker read operations and shorter delays due to the increased carrier mobility and decreased leakage currents [30]. Fig. 4 illustrates the relationship between write delay and read delay in a CMOS based 8T SRAM. In both instances of write delay and read delay, the delay time increases whenever the temperature rises. When the temperature approaches 500 K, however, the curve indicates that the delay is decreasing. Monitoring the variance in the working efficiency of a transistor as a consequence of temperature enables its measurement. Temperature interferes with the operating current and leakage current through the transistor. The circulation of discharge in the SRAM cell’s transistors increases the ambient temperature elevates. The enhanced leakage current affects the stability of both the high and low logic states, leading to an increase in delay.

    Write delay and read delay vs different temperature of CMOS based 8T SRAM.

    Figure 4.Write delay and read delay vs different temperature of CMOS based 8T SRAM.

    Fig. 5 illustrates the correlation between the power consumption and temperature of an 8T SRAM cell. Temperature fluctuations have a major impact on the power consumption of CMOS based 8T SRAM cells. With the rise in temperature, the subthreshold leakage currents in CMOS transistors grow exponentially because of the increased production of thermal carriers [31]. This results in a significant increase in static power consumption. The impact of this phenomenon is more evident when the device is in standby mode, as power leakage becomes the dominant factor in the power consumption profile. Furthermore, the presence of gate leakage currents exacerbates static power loss when temperatures are high. The dynamic power consumption, mainly linked to the charging and discharging of capacitive loads during switching, has a relatively lower sensitivity to temperature. However, elevated temperatures can significantly diminish carrier mobility, resulting in an increase in the effective resistance of the transistors and interconnects, thereby modestly elevating dynamic power consumption [32]. The short-circuit power, which occurs when both PMOS and NMOS transistors conduct simultaneously during switching, also increases with temperature because of quicker switching transitions and lower threshold voltages.

    Power consumption vs temperature of CMOS based 8T SRAM.

    Figure 5.Power consumption vs temperature of CMOS based 8T SRAM.

    The power delay product (PDP) is a crucial measure for assessing the effectiveness of SRAM cells, encompassing both the power usage and the operational delay (for write or read). The write delay of the SRAM cell lengthens as temperature rises, mostly because of decreased carrier mobility and slower transistor switching rates. Simultaneously, the amount of power used during writing processes increases because of higher levels of leakage currents and switching activities. The combined factors result in a significant increase in the write PDP at elevated temperatures, suggesting worse energy efficiency during write operations. Similarly, the time it takes to read likewise increases with greater temperatures, indicating a positive correlation between temperature and delay. This can be due to the slower discharge of the bit line and the decreased responsiveness of the sensing amplifiers. As the temperature rises, the increased power consumption and longer read delays lead to a higher read PDP, indicating worse efficiency of read operations under thermal stress. Fig. 6 highlights the correspondence among write and read PDP for different temperatures, where PDP is almost constant, however the value jumps after 400 K and reaches its maximum at 600 K. Increasing the temperature positively impacts the device’s leakage current. This enhanced leakage current is susceptible to a rise in the SRAM cell’s inanimate power consumption. The temperature dependence of the write and read energy delay product (EDP) is depicted in Fig. 7 where we can find that read EDP is almost 3 times higher than write EDP. EDP is a metric that quantifies the energy efficiency of the SRAM cell by considering both the overall energy consumption and the time delay during operation. As the temperature rises, both the amount of energy used during write operations and the time it takes to complete a write operation increase. The increase in energy is mostly caused by higher static power consumption resulting from leakage currents, whereas the delay increase is attributed to reduced switching rates. As a result, the write EDP shows a significant rise at elevated temperatures, suggesting that the energy efficiency of write operations decreases with increasing temperature. The rise in read EDP is caused by the temperature-induced increase in read delay, as well as the additional energy required owing to greater leakage and switching power. These findings indicate that when temperature rises, the energy efficiency of read operations diminishes due to the combined effects of increased latency and energy consumption under thermal circumstances.

    PDP vs temperature of CMOS based 8T SRAM.

    Figure 6.PDP vs temperature of CMOS based 8T SRAM.

    EDP vs temperature of CMOS based 8T SRAM.

    Figure 7.EDP vs temperature of CMOS based 8T SRAM.

    3.3 Effect of tube diameter and tube position on the CNTFET based 8T SRAM cell

    Multiple nanotubes share a single gate in CNTFET. The standard model accounts for the impact of charge screening among several nanotubes in an identical device. The uniform model assumes that all CNTs in the device have about the same charge screening properties. Two CNTs at both ends of the device (each with only one adjacent nanotube) and n-2 CNTs in the middle (each of which has two neighbors on each side) are autonomously separated from one another in the standard CNTFET model. The charge screening effects are smaller near the extremities of the CNTs than they are in the center. Therefore, this model is the gold standard since it more precisely takes into consideration charge screening impacts on drive current and the performance of the device [33]. The whole CNTFET device concept is realized with a three-tiered hierarchical structure. Here the number of CNTs used is 3. CNTFET’s base-level functionality is modeled in carbon nanotube field effect transistor level 1 (CNTFET_L1). The imperfections of the device are described in carbon nanotube field effect transistor level 2 (CNTFET_L2). There is a single CNT behind the gate on the initial two floors. The CNTFET device interaction with CNTFET circuits is modeled at the highest level, carbon nanotube field effect transistor level 3 (CNTFET_L3) . Several CNTs in a single device, together with parasitic gate capacitance and screening from nearby CNTs, are addressed here [34]. The gate control over the channel is affected by electrostatic contact with neighboring CNTs or other components of the device, leading to screening effects. The subthreshold swing as well as leakage currents might both be negatively affected by it. To improve device efficiency and reduce leakage, it is possible to limit CNTFET screening effects by employing a high-κ dielectric material or by adjusting the gate-to-channel distance.

    $ {C}_{\mathrm{e}\mathrm{f}\mathrm{f}}=\frac{{\text{ε}}}{{d}_{\mathrm{s}\mathrm{c}\mathrm{r}\mathrm{e}\mathrm{e}\mathrm{n}\mathrm{i}\mathrm{n}\mathrm{g}}} $ ()

    where Ceff is the effective capacitance, ε is the dielectric constant, and dscreening is the distance between the CNTs or gate and channel.

    CNT positioning and orientation in CNTFET based SRAM is crucial for the device’s efficiency. Among the many undesirable outcomes that can result from CNT spacing variations or misalignment is an increase in parasitic capacitance and resistance, which in turn has a negative impact on switching speed as well as delay. The gate’s electrostatic influence on the channel is reduced when it is not properly aligned, leading to increased leakage currents and power consumption, especially while the device is in standby [35]. Inconsistent behavior of SRAM cells, lower noise margins, and possible failure during read and write operations can result from this misalignment, which can cause unpredictability in the threshold voltage and drive current. According to most simulations, even little changes in the placement of CNTs can lead to noticeable spikes in latency and power consumption. To tackle these problems, one may use modern manufacturing processes such enhanced chemical vapor deposition to align CNTs better and multi-tube CNTFET designs to make them more resistant and less sensitive to mistakes in tube placement. But even with these methods, getting everything to line up perfectly in mass production is still difficult, so we need to look into design-level solutions like error correction and redundancy to keep SRAM performance dependable [36]. Specifically, changes in temperature can have a major effect on the mobility, threshold voltage, and leakage currents of CNTFETs. Generally, phonon scattering increases with temperature, limiting carrier mobility, lowering the threshold voltage increases leakage and decreases drive current, and so forth. As a result of lowered mobility caused by higher temperatures, switching speeds might decrease, resulting in longer propagation delays. An exponential increase in leakage current, which in turn increases static power consumption in standby mode, can be caused by higher temperatures.

    When the tube position is 0 under the same gate, it indicates that the tube in the middle is the tube that is positioned midway between two neighbors. When the tube position is 1, it indicates that the tube is at the device’s border and only observes one adjacent CNT [26]. Figs. 8 and 9 display that if we increase the tube diameter of the device then it will decrease the write and read delay of the device. Additionally, the tube position has a slight impact on the delay. When the tube position is 1, it will give a slightly higher value of the delay compared to tube position 0. Fig. 10 represents the total power consumption of CNTFET based 8T SRAM with different tube diameter & tube position. The increasing pattern of the tube diameter provides higher leakage current, as a result, the power consumption will be higher for the larger tube diameter of the CNT. Fig. 11 shows the comparative analysis of CMOS and CNTFET based SRAM power consumption analysis where CNTFET based SRAM results as an efficient device. The size of CNTs affects the energy gap of the CNTFET, which subsequently impacts the movement of charge carriers. Increasing the diameter of the tube reduces the bandgap, which in turn increases the mobility of carriers. This amplifies the driving current, hence decreasing the time it takes to write and read data in the SRAM cell. On the other hand, when the tube diameters are reduced, the bandgap increases, which in turn decreases the mobility of carriers and increases the delay [37]. The arrangement of CNTs within the CNTFET structure impacts the electrostatic interaction between the gate and the channel. Strategically placing the CNTs in the right location allows for effective control of the gate, which in turn minimizes the unwanted capacitances and ultimately decreases the time it takes to write and read data. Suboptimal positioning of the CNTs can result in diminished gate control, which in turn can cause heightened parasitic effects, hence impeding the speed of write/read operations [38].

    Write delay vs tube diameter 8T CNTFET based SRAM with multiple tube positions.

    Figure 8.Write delay vs tube diameter 8T CNTFET based SRAM with multiple tube positions.

    Read delay vs tube diameter of 8T CNTFET based SRAM with multiple tube positions.

    Figure 9.Read delay vs tube diameter of 8T CNTFET based SRAM with multiple tube positions.

    Power consumption vs tube diameter of 8T CNTFET based SRAM with multiple tube positions.

    Figure 10.Power consumption vs tube diameter of 8T CNTFET based SRAM with multiple tube positions.

    Comparative analysis of CMOS and CNTFET based SRAM in terms of power consumption for different tube diameter and temperature analysis.

    Figure 11.Comparative analysis of CMOS and CNTFET based SRAM in terms of power consumption for different tube diameter and temperature analysis.

    Fig. 10 represents that if we increase the tube diameter of the device, then it will decrease the power consumption of the device. Additionally, the tube position has a slight impact on the power consumption. When the tube position is 1, it will give a slightly higher value of the power consumption compared to tube position 0. When the tube diameter is 1.4877 nm with tube position 0, the device consumes 4.422 nW of power; when the tube position is 1, it consumes 4.711 nW of the power. It indicates that tube position 1 consumes more power. CNTs with larger diameters, due to their narrower bandgaps, exhibit greater leakage currents, leading to an increase in static power consumption. Nevertheless, the dynamic power consumption may decrease as a result of accelerated switching speeds facilitated by increased mobility. In contrast, smaller diameters with greater bandgaps have lower leakage currents, which might potentially decrease static power consumption. However, they may have higher dynamic power consumption due to slower processes [39]. The arrangement of CNTs also impacts the total capacitance of the device. Inadequate placement can result in an increase in parasitic capacitance, which in turn leads to elevated levels of dynamic power consumption [40,41]. Furthermore, if CNTs are strategically placed in greater proximity to the source or drain areas, it might lead to an escalation in leakage currents, resulting in an increase in static power consumption [42].

    Figs. 12 and 13 illustrate the dependence of write and read PDP on tube diameter and position. Both write and read PDP exhibit an ascending trend. In the case of a write operation, if we change the diameter of the tube from 1.0179 nm to 1.95575 nm, the PDP will increase from 10.69 zJ to 930.13 zJ for tube position 0 and from 11.09 zJ to 929.31 zJ for tube position 1 (as seen in Fig. 13). In the case of the read operation from Fig. 13, we can see that if we change the tube diameter from 1.0179 nm to 1.95575 nm, the PDP will increase from 10.69 zJ to 931.25 zJ for tube position 0 and from 11.12 zJ to 931.82 zJ for tube position 1. This result indicates that for smaller tube diameters, tube position 0 has less PDP than tube position 1, whereas for large tube diameters, the opposite is true. During the read operation, regardless of whether the tube diameter is large or small, tube position 1 results in a marginally higher PDP. Additionally, we can also determine that read PDP is greater than write PDP for various tube diameters and tube positions.

    Write PDP vs tube diameter of 8T CNTFET based SRAM with multiple tube positions.

    Figure 12.Write PDP vs tube diameter of 8T CNTFET based SRAM with multiple tube positions.

    Read PDP vs tube diameter of 8T CNTFET based SRAM with multiple tube positions.

    Figure 13.Read PDP vs tube diameter of 8T CNTFET based SRAM with multiple tube positions.

    For the 8T SRAM CMOS technology in the room temperature (300 K), the write delay is 20.69 ps, and read delay is 54.96 ps. On the other hand, for the CNTFET based 8T SRAM cell using a tube diameter of 1.4877 nm, the result is a write delay of 5.118 ps and read delay of 5.134 ps. Also, the power consumption for CMOS based SRAM cell is 25.38 nW, and for CNTFET technology the power consumption is 4.711 nW. CNTFET based SRAM is almost 4 times faster in terms of write delay and 10 times faster in terms of read delay compared to CMOS technology. Also, the CNTFET based 8T SRAM cell is 5 times less power consumption compared to CMOS technology. We also found the write/read PDP for CMOS 8T SRAM cell is 0.506 aJ and 1.646 aJ, respectively. On the other hand, for CNTFET based 8T SRAM cell write/read PDP is 24.11 zJ and 24.19 zJ, respectively.

    In Table 3, we have presented different parametric performance analyses of SRAM technology, such as write delay, read delay, power consumption, and PDP value. Here, we have analyzed performance metrics for CNTFET, CMOS, fin field-effect transistor (FinFET), and tunnel field-effect transistor (TFET) based SRAM.

    TechnologyWrite delayRead delayPower consumptionPDP
    CNTFET (in this work)4.94 ps4.951 ps1.971 nW10.68 zJ
    FinFET [40,43]0.75 ns2.85 ns12.52 nW4.53 nJ
    TFET [41,44]3.554 ns2.292 ns0.412 pW
    CMOS (in this work)41.2 ps16.16 ps13.7 nW64.84 zJ

    Table 3. Comparative analysis between different technologies SRAM.

    4 Conclusions

    This study presents an investigation of the performance of 8T SRAM cells based on CNTFET and CMOS technologies. This investigation examines the impact of the position of CNTs within a given gate. The performance is analysed in two distinct positions of the tubes. In short, CNTFET has exhibited remarkable promise when compared to traditional CMOS based devices. CNTFET provides several advantageous properties, including high carrier mobility, exceptional electrical characteristics, and the potential for decreased power consumption. CNTFETs are being contemplated for utilization in the advancement of SRAM cells, among various other applications, due to their distinctive characteristics. CNTFET based SRAM holds significant potential because of its exceptional performance and little power consumption. The high carrier mobility of CNTs enhances the read/write timings of SRAM by enabling faster switching rates and reduced propagation delays. Furthermore, the reduced power consumption of SRAM cells during standby operations can be attributed to the ability to attain high ION/IOFF ratios through the utilization of CNTFETs. Furthermore, CNTFETs exhibit superior scalability compared to traditional metal-oxide-semiconductor field-effect transistor (MOSFETs), potentially enabling the incorporation of additional SRAM cells inside a given physical structure. As a result of the improved integration density, there has been a corresponding rise in both memory capacity and overall performance.

    Disclosures

    The authors declare no conflicts of interest.

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    Mahamudul Hassan Fuad, Md Faysal Nayan, Sheikh Shahrier Noor, Rahbaar Yeassin, Russel Reza Mahmud. Comprehensive performance analysis of CMOS and CNTFET based 8T SRAM cell[J]. Journal of Electronic Science and Technology, 2025, 23(2): 100306
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