Mixed-Criticality Flows Scheduling Algorithm for Crossbar Switches

LIN Wan-qing; LI Qiao; ZHAO Lu-xi; WANG Tong

doi:10.3969/j.issn.1671-637x.2016.07.002

[1] SAE Aerospace. SAE AS6802 Time-triggered Ethernet［S］. ［S. l. ］: SAE International, 2011.

[3] CHRYSOS N, KATEVENIS M. Weighted fairness in buffered crossbar scheduling［C］//IEEE HPSR, Torino, Italy, 2003: 17-22.

[4] JAVIDI T, MAGILL R, HRABIK T. A high-throughput sche-duling algorithm for a buffered crossbar switch fabric［C］//Proceeding IEEE ICC′2001, Helsinki, 2001: 1586-1591.

[5] CHANG C S, CHEN W J, HUANG H Y. On service guarantees for input-buffered crossbar switches: a capacity decomposition approach by Birkhoff and Von Neumann［C］//IWQoS99, Seventh International Workshop on Quality of Service, London, 1999: 79-86.

[6] CHANG C S, LEE D S, JIY Y S. Load balanced Birkhoff-Von Neumann switches, part I: one-stage buffering［J］. Computer Communications, 2002, 25(6): 611-622.

[7] MCKEOWN N. The iSLIP scheduling algorithm for input-queued switches［J］. IEEE/ACM Transactions on Networking, 1999, 7(2): 188-201.

[8] STEINER W. Synthesis of static communication schedules for mixed-criticality systems［C］//14th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing Work-shops(ISORCW). IEEE, Newport Beach, 2011: 11-18.

[9] TAMAS-SELICEAN D, POP P, STEINER W. Synthesis of communication schedules for TTEthernet-based mixed-criticality systems［C］//Proceedings of the 8th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, ACM, 2012: 473-482.

[10] TAMIR Y, FRAZIER G L. High-performance multi-queue buffers for VLSI communications switches［M］. ［S. l. ］: IEEE Computer Society Press, 1988.

[11] MRKKITTIKUL A, MCKEOWN N. A practical scheduling algorithm to achieve 100% throughput in input-queued switches［C］//INFOCOM98. Seventeenth Annual Joint Conference of the IEEE Computer and Communications Societies Proceedings IEEE, San Francisco, 1998: 792-799.

[14] ZHAO L X, XIONG H, ZHENG Z, et al. Improving worst-case latency analysis for rate-constrained traffic in the time-triggered ethernet network［J］. IEEE Communications Letters, 2014, 18(11): 1927-1930.

[15] STEINER W. An evaluation of SMT-based schedule synthesis for time-triggered multi-hop networks［C］//31st. Real-Time Systems Symposium(RTSS). IEEE, San Diego, 2010: 375-384.

[16] GUPTA P, MCKEOWN N. Designing and implementing a fast crossbar scheduler［J］. IEEE Micro, 1999, 19(1): 20-28.