Subthreshold analog techniques

IEEE J. Solid-State Circuits, 2019, doi: 10.1109/JSSC.2018.2889847

Low power is a fundamental requirement in state-of-the-art IC designs, where lower and scalable supply voltages are demanded due to the power benefits of digital circuits under near- and sub-threshold supply voltages. The ultra-low voltage design is also driven by technology scaling as well as leakage and reliability considerations. While analog circuits with weak-inversion transistors benefit from high g_m/I_D due to the exponential characteristics of the V_GS versus I_D curve in weak inversion, the shrunk voltage headroom and signal swing limit signal-to-noise ratio fundamentally, and the linearity of transconductance becomes worse. In addition, the decreased intrinsic gain of downscaled planar transistors makes it difficult to build high gain analog blocks. It is thus very challenging to design high-linearity and high-precision analog circuits under near- and sub-threshold supply voltages, where operational transconductance amplifiers are fundamental. Though several approaches have been proposed to replace OTAs in particular analog systems by, e.g., time-domain circuits, dynamic amplifiers, ring amplifiers, zero-crossing based circuits, etc., OTAs remain indispensable due to their linear operation in closed-loop systems.

The team of researchers from University of Electronic Science and Technology of China presented an evolution process of implementing conventional structures with inverters, allowing ultra-low voltage operation with increased flexibility in adopting traditional circuit techniques. Based on the proposed inverter-based elementary structure and CMFB, both the Miller-compensated (MC) OTA and the feedforward-compensated (FFC) OTA achieved significantly improved performance as compared to previous works. The proposed amplifier techniques were verified in ΔΣ modulator (DSM) design, with MC-OTA for a DT-DSM and FFC-OTA for a CT-DSM, both fabricated in a 0.13 μm CMOS. The 0.3 V DT-DSM achieved 74.1 dB SNDR, 83.4 dB SFDR and 20 kHz bandwidth with 79.3 μW power, resulting in a Schreier FoM of 158 dB. The 0.3 V CT-DSM achieved 68.5 dB SNDR, 82.6 dB SFDR and 50 kHz bandwidth with 26.3 μW power, leading to a Schreier FoM of 161 dB. Both DSMs exhibit highly competitive performance among sub-0.5 V designs, validating the proposed subthreshold amplifier techniques.

Nanjian Wu (Institute of Semiconductors, CAS, Beijing, China)

doi: 10.1088/1674-4926/40/2/020204