Design and Implementation of DMA Transmission with PCIe Bus Based on FPGA

ZOU Chen; GAO Yun

doi:10.3969/j.issn.1671-637x.2015.07.017

Journals >Electronics Optics & Control >Volume 22 >Issue 7 >Page 84 > Article

Electronics Optics & Control
Vol. 22, Issue 7, 84 (2015)

Design and Implementation of DMA Transmission with PCIe Bus Based on FPGA

ZOU Chen and GAO Yun

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[in Chinese]

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DOI: 10.3969/j.issn.1671-637x.2015.07.017 Cite this Article

ZOU Chen, GAO Yun. Design and Implementation of DMA Transmission with PCIe Bus Based on FPGA[J]. Electronics Optics & Control, 2015, 22(7): 84 Copy Citation Text

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References

[5] PCI Special Interest Group.PCI Express base specification revision 1.0a［EB/OL］.［2014-07-21］.http://netyi.net/Book.

[6] Xilinx.LogiCoreTM IP endpoint for PCI Express V3.7 user guide［EB/OL］.［2014-07-21］.http://www.xilinx.com.

[9] STILIADIS D,VARMA A.Selective victim caching:a method to improve the performance of direct-mapped caches ［J］.IEEE Transactions on Computers,2007,46(5):603-610.

ZOU Chen, GAO Yun. Design and Implementation of DMA Transmission with PCIe Bus Based on FPGA[J]. Electronics Optics & Control, 2015, 22(7): 84

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