The rapid development of digital information technology has placed higher requirements on the transmission capacities and energy consumption of data centers. Mode multiplexing/demultiplexing (MUX/DEMUX) technology based on silicon-on-insulator (SOI) platforms is highly promising for realizing on-chip data transmission with high capacity, low loss, and low cost and has thus become a research hotspot in scientific research and industry. As the basic unit of the MUX/DEMUX technique, mode converters with high conversion efficiency, low loss, and larger bandwidth are indispensable. Thus far, most of the reported mode converters are realized by using specific structures such as directional couplers, asymmetric Y-junctions, multimode interference couplers, and asymmetric directional couplers. The designs of these mode converters rely on designer experience and require considerable time to optimize structural parameters. In addition, when the design target (target mode) changes, redesigning and optimizing the structure are often necessary, where the repetitive work leads to low design efficiency. However, inverse design of device structures through intelligent algorithms can effectively reduce the design costs of devices and improve design efficiency. In this study, a highly efficient mode converter based on edge shape optimization is presented on an SOI platform. The footprint of the device is 10.0 μm×1.5 μm. TE₀-TE₁ converter has the advantages of high conversion efficiency, high extinction ratio, low insertion loss, and high fabrication tolerance within a larger bandwidth using an adjoint method. Furthermore, the mode converter is fabricated using a commercial multi-project wafer (MPW) program, and measurements are executed using a novel on-chip test structure.

First, the initial structure of the device was designed while 100 discrete boundary optimization points were simultaneously inserted into the top boundary of the design region of the TE₀-TE₁ device. The edge of the mode converter was then optimized by adjusting the position of the optimization points in the y-axis direction using the adjoint method. After 30 iterations, the optimal positions of the optimization points were obtained in the y-axis direction. The boundary curve was defined by connecting the points using spline interpolation fitting. The number of iterations was effectively reduced and design efficiency was improved using the adjoint method. Based on the effects of the fabrication process on device performance, the fabrication tolerance of mode converters was investigated by adjusting the widths of devices, where the change in width was within ±20 nm. In addition, the prepared devices were measured using an on-chip test structure to characterize the high performance of TE₀-TE₁ converter.

For TE₀-TE₁ converter, the conversion efficiency reaches 99.6% at the central wavelength of 1550 nm, while the extinction ratio reaches 31.2 dB. The insertion loss is calculated as 0.01 dB (Fig. 3). As the wavelength varies from 1500 nm to 1600 nm, the conversion efficiency and extinction ratio can be maintained at greater than 96.6% and 15.7 dB, respectively, whereas the insertion loss is maintained at less than 0.14 dB (Fig. 3). It is noteworthy that the optimized devices are insensitive to wavelength variations. The fabrication tolerance of the devices was also analyzed. For TE₀-TE₁ converter, the conversion efficiency and extinction ratio can be maintained at greater than 97.2% and 16.5 dB, respectively, whereas the insertion loss is less than 0.12 dB under a width variation of ±20 nm at 1550 nm (Fig. 4). These results show that the optimized devices are highly tolerant to fabrication tolerance. Experimental results show that the output power of up, down, and middle ports is -3.5 dB, -3.0 dB, and -16.8 dB at 1550 nm, respectively. As the wavelength varies from 1500 nm to 1560 nm, the output power of the up and down ports is maintained at greater than -4.3 dB and -3.8 dB, respectively (Fig. 6). The output power of up and down ports is basically the same. The output power of the middle port is less than -15.2 dB (Fig. 6). It can be proved that the output mode of the device is TE₁. In the 60-nm bandwidth range, the conversion efficiency of TE₀-TE₁ converter is greater than 90%, and the insertion loss is less than 0.4 dB (Fig. 6). To compare the performances of mode converters with those in the forefront, this study reports on the mode converters designed using inverse design methods over the last five years. Results show that the TE₀-TE₁ converter designed in this study has advantages in terms of bandwidth and loss.

A compact mode converter with large bandwidth, high conversion efficiency, high extinction ratio, low insertion loss, and high fabrication tolerance is experimentally demonstrated. The adjoint method allows for a highly effective design of the mode converter. Simulation results show that the conversion efficiency and extinction ratio are greater than 96.6% and 15.7 dB, respectively, and the insertion loss is less than 0.14 dB within the wavelength range of 1500 nm to 1600 nm. A novel test structure is designed on the chip to characterize the output TE₁ mode, with results showing a conversion efficiency maintained at greater than 90% and insertion loss at less than 0.4 dB within a 60-nm bandwidth. The proposed design method can be extended to realize the conversion of arbitrary modes, thus providing a means for the efficient design of high-performance on-chip mode converters.