With the increasing bandwidth demands for high-speed data center interconnection (DCI) and passive optical networks (PONs), the intensity modulation-direct detection (IM-DD) technique is becoming difficult to maintain with low system costs and power consumption characteristics. Due to the limitation of the modulation dimension, it is required to adopt multilane configuration with a more complicated digital signal processing (DSP) technique and a higher electrical bandwidth^[1,2]. Because of the low tolerance to chromatic dispersion (CD), polarization mode dispersion (PMD), and four-wave mixing, IM-DD cannot continuously scale optical lanes and baud rate^[3]. According to the comparison of 400 G IM-DD and coherent detection for intra-data center optical interconnects, the latter shows higher energy efficiency based on the current commercial technique^[4]. Developed from long-haul high-speed transmission, the coherent technique has superior performance in short-distance applications after linear and nonlinear impairment compensation^[5,6].

However, the conventional coherent transceivers require DSP algorithms with high computational complexity, resulting in high cost and high power consumption, which is unacceptable for short-reach coherent DCI and PON. The low-complexity DSP technique is highly desired in such a cost-sensitive market^[7–12]. As one of the most complicated DSP modules^[13], the adaptive channel equalization (ACE) is typically realized by N-tap complex-valued (CV) $2\times 2$ multiple input multiple output (MIMO) configurations or real-valued (RV) $4\times 4$ MIMO configurations based on finite impulse response (FIR) filters, which involves a large number of multiplication operations. Its main function is to perform polarization demultiplexing, compensating for linear channel impairments caused by intersymbol interference (ISI), residual CD, and PMD. Due to the limited linear channel impairments in short-reach transmission, the ACE can be simplified with a slight performance penalty.

In order to reduce the complexity of ACE, the conventional algorithm structure can be divided into two sections, which consist of a one-tap CV $2\times 2$ MIMO in the first section and two parallel N-tap CV FIR filters in the second section^[14]. Therefore, the input signals are first polarization-demultiplexed and then equalized separately. As a result, the multiplier consumption can be reduced by more than 40%, and the performance is comparable to the conventional ACE algorithm. The multiplier consumption can be further reduced by replacing the two N-tap CV FIR filters with RV FIR filters, and the tolerance of in-phase and quadrature skew of this structure is improved by adding a post-three-tap T-spaced $4\times 4$ real-valued MIMO FIR filter^[15]. To realize real-time DSP implementation, we proposed a novel inverted structure to further reduce the complexity of the parallel processing system^[16]. By replacing the CV filters with RV filters and adjusting the real/imaginary filters with different tap lengths, the complexity can be further reduced with high robustness against timing skew^[17].

In this Letter, we propose and experimentally demonstrate a multiplier-simplified ACE. The data processing is conducted based on a hardware-efficient logic unit, such as a shifter and an adder, rather than a conventional multiplier. Based on the structure of conventional ACE, the simplifying method is verified. For different modulation formats, the performance of the proposed simplified ACE can be adjusted by employing different numbers of shifters. In the offline experiment, the performances of 64 Gbaud polarization division multiplexed quadrature phase shift keying (PDM-QPSK), 16-quadrature amplitude modulation (QAM), and 64-quadrature amplitude modulation (64QAM) are verified. In the case of PDM-16QAM within 10.8 km transmission, the performance penalty can be limited to less than 0.2 dB by the proposed ACE, compared with the conventional method. Furthermore, based on our 10 Gb/s real-time coherent optical transceiver, the proposed ACE is built up in the field-programmable gate array (FPGA), and the performance is verified in the 10.8 km fiber transmission experiment.

In the DSP of a short-reach coherent receiver, bulk CD compensation is unnecessary. Except for forward error correction (FEC) decoding, ACE is one of the most power consumption parts, which requires a large number of multipliers. As shown in Fig. 1, ACE can adaptively realize signal equalization, polarization demultiplexing, and downsampling based on the processing mainly consisting of multiplications between input data samples and equalization coefficients. The ACE process and coefficient update are expressed as $$E_{\mathrm{out}}^x={\sum }_{i=1}^n{F}^{xx}(i)E_{\text{in}}^x(i)+{\sum }_{i=1}^n{F}^{yx}(i)E_{\text{in}}^y(i),$$(1)$$E_{\mathrm{out}}^y={\sum }_{i=1}^n{F}^{xy}(i)E_{in}^x(i)+{\sum }_{i=1}^n{F}^{yy}(i)E_{\text{in}}^y(i),$$(2)$$F^{xx}=F^{xx}+4\mu {\epsilon }_x{E}_{\mathrm{out}}^x{[E_{\text{in}}^x]}^{*},$$(3)$$F^{yx}=F^{yx}+4\mu {\epsilon }_x{E}_{\mathrm{out}}^x{[E_{\text{in}}^y]}^{*},$$(4)$$F^{xy}=F^{xy}+4\mu {\epsilon }_y{E}_{\mathrm{out}}^y{[E_{\text{in}}^x]}^{*},$$(5)$$F^{yy}=F^{yy}+4\mu {\epsilon }_y{E}_{\mathrm{out}}^y{[E_{\text{in}}^y]}^{*},$$(6)where $E_{\text{in}}^x$ and $E_{\text{in}}^y$ are the inputs of $x$ and $y$ polarizations, $E_{\mathrm{out}}^x$ and $E_{\mathrm{out}}^y$ are the outputs of ACE, $F^{xx}$, $F^{yx}$, $F^{xy}$, and $F^{yy}$ are the ACE coefficients, $n$ is the tap length of the filter, $\mu$ is the step index, and $\epsilon$ is the error factor. According to the length of the filter, $4n$ complex multiplication operations are required in Eqs. (1) and (2).

In high-speed parallel real-time processing systems, such a conventional ACE will consume a lot of resources and power. It is worth mentioning that the coefficient value can be expressed between $-1$ and 1. We experimentally transmit 64 Gbaud PDM-QPSK, PDM-16QAM, and PDM-64QAM signals over 10.8 km standard single-mode fiber (SSMF). The resultant coefficient value of the 27-tap ACE is shown in Fig. 2. In order to reflect the value distribution of each format, all real and imaginary components including $F^{xx}$, $F^{xy}$, $F^{yx}$, and $F^{yy}$ from 10 random measurements are plotted together for different formats in Fig. 2.

According to the characteristic of numerical distribution, the multiplication operation between input data samples and coefficient can be replaced by a few shifters and adders with little performance degradation in short-reach distance. Through M-bit right-shift, approximately ${1/2}^{\mathrm{M}}$ of the input data can be obtained. Then, according to the coefficient, an approximate multiplication result can be easily obtained by addition of reasonable serials from ${1/2}^1$ to ${1/2}^{\mathrm{M}}$ of input data. The calculation processing can be expressed as $$D_{\mathrm{out}}=\mathrm{Sign}(F)·{\sum }_{i=1}^{\mathrm{M}}[F_i·(D_{\text{in}}\gg i)],$$(7)where $D_{\text{in}}$ and $D_{\mathrm{out}}$ refer to the input and output data. ($D_{\text{in}}\gg i$) is the $i$-bit right-shift result of $D_{\text{in}}$. $\mathrm{Sign}(F)$ is the sign ($-1$ or 1) of coefficient $F$. $F_i$ is the enable bit (0 or 1), which controls whether ($D_{\text{in}}\gg i$) is presented in the adder. [${\mathit{F}}_1\dots {\mathit{F}}_{\mathrm{M}}]$ can be obtained from an M-bit left-shift of F, where the most significant bit (MSB) is F₁ and the least significant bit (LSB) is ${\mathit{F}}_{\mathrm{M}}$. Increasing M can improve the calculation accuracy but results in more DSP consumption. Decreasing M can reduce DSP consumption but will increase calculation errors. Trading off between the performance and cost, the simplification penalty can be controlled within an acceptable range by selecting an appropriate M according to different modulation formats.

The proposed multiplier-simplified ACE is first experimentally verified by the offline test platform, as shown in Fig. 3. At the transmitter side, a free-running external cavity laser (ECL) with a linewidth of 100 kHz is operated at 1550 nm and output power of 13 dBm. Then the optical carrier is sent into a double polarization in-phase quadrature modulator (DP-IQM, Fujitsu FTM7992HM). A 64 Gbaud electrical signal from an arbitrary waveform generator (AWG, Keysight M8196A) running at 92 GSa/s is amplified by an electrical driver and then loaded into the DP-IQM. The modulated optical signal is amplified by an erbium-doped fiber amplifier (EDFA) and then launched into the SSMF with a length of 10.8 km for transmission.

At the receiver side, the optical signal is first adjusted by a variable optical attenuator (VOA) and then fed into a coherent receiver, which consists of discrete 90-degree hybrid and balanced photodetectors (BPDs). Another ECL with a linewidth of 100 kHz as the local oscillator (LO) is operated at 1550 nm and output power of 13 dBm. An 8-bit digital sampling oscilloscope (DSO, Lecroy 10-36Zi-A) operating at 80 GSa/s is used to sample the detected electrical signal. The AWG and DSO share the same reference clock to avoid clock data recovery (CDR). In the offline DSP, the sampled data is first resampled to 128 GSa/s for two samples per symbol. After frame synchronization, the frequency offset is estimated and compensated based on the pilot. The data is processed in the ACE with 27-tap CV $2\times 2$ MIMO structure. A direct decision-least mean square (DD-LMS) algorithm is used to update the coefficients. Then, carrier phase recovery is performed to compensate for the phase noise. Finally, the bit error ratio (BER) is obtained after symbol decision and error number counting.

We load 64 Gbaud PDM-QPSK, PDM-16QAM, and PDM-64QAM in the experiment, respectively, and investigate the effects of optical receiver power on the proposed ACE with different calculation accuracies controlled by M. The result is compared with the performance of a conventional ACE. As shown in Fig. 4(a), in the case of 64 Gbaud PDM-QPSK, with $\mathrm{M}=6$, the performance penalty of the proposed ACE is about 0.5 dB at HD-FEC threshold $3.8\times {10}^{-3}$. Increasing M to 7 can reduce the penalty to 0.2 dB, and conversely, decreasing M to 5 will increase the penalty to 1.5 dB. In the case of 64 Gbaud PDM-16QAM, as shown in Fig. 4(b), the performance penalty can be controlled to less than 0.5 dB with $\mathrm{M}=7$ and 0.2 dB with $\mathrm{M}=8$ at the HD-FEC threshold. When M is reduced to 6, the performance penalty increases to nearly 1.3 dB. For the modulation format of PDM-64QAM, as shown in Fig. 4(c), the penalty can be controlled within 0.5 dB by selecting M as 8 at a C-FEC threshold of $1.25\times {10}^{-2}$. From the results measured in different modulation formats, the corresponding reasonable multiplier-simplified levels can be obtained in the case of 10.8 km transmission. To maintain the simplification penalty within 0.5 dB, the optimum values of parameter M are recommended to be 6, 7, and 8 for PDM-QPSK, PDM-16QAM, and PDM-64QAM, respectively. This trend reflects the requirement for higher calculation accuracy for high-order modulation formats.

Then, for 64 Gbaud PDM-16QAM, we further investigate the receiver sensitivity penalty of the proposed ACE at the HD-FEC threshold at different transmission distances (0, 2.7, 5.5, and 10.8 km), compared with the conventional method. As shown in Fig. 5, with $\mathrm{M}=7$ or 8, the receiver sensitivity penalty within 10.8 km maintains a stable value. In the case of $\mathrm{M}=7$, the penalty is less than 0.5 dB. Increasing M to 8 can reduce the penalty within 0.2 dB. When M is reduced to 6, the penalty for the transmission distance less than 5.5 km is about 1 dB. As the transmission distance increases to 10.8 km, the penalty increases to about 1.3 dB. Longer transmission distance introduces more channel impairments, especially CD. The result shows a weakening of CD compensation capacity as the calculation accuracy decreases.

Based on the fiber like, a 10 Gb/s PDM-QPSK real-time coherent transceiver^[18] is introduced instead of the offline transmitter and receiver, as shown in Fig. 6.

At the transmitter side, a free-running external cavity laser (ECL) with a linewidth of 100 kHz is operated at 1550 nm and output power of 13 dBm. Four independent $2^{23}-1$ pseudorandom bit sequences (PRBSs) are generated at 2.5 Gb/s in the FPGA. After being amplified by the electrical driver, the electrical signals are then launched into the DP-IQM to generate an optical PDM-QPSK signal. The modulated optical signal is amplified by an EDFA and then fed into the 10.8 km SSMF link.

At the receiver side, the optical signal is first adjusted by a VOA and then received by an ICR. The LO laser with a linewidth of 100 KHz operates at an output power of 13 dBm. After coherent detection, the electrical signal is sampled twice per symbol by four ADCs (E2V EV8AQ160, 8-bit resolution), with a sampling rate of 5 GSa/s. Finally, the sampled signals are processed inside the FPGA (Altera 5SGSMD8K) with the clock of 156.25 MHz.

In the FPGA, all ADC output serial signals are deserialized into 32 parallel tributary channels. Therefore, $32\times 2$ channels of complex data from $x$ and $y$ polarizations are processed in parallel in a seven-tap ACE module, which means that 448 complex multipliers are required. A complex multiplier can be consisted of four real multipliers and two adders. The multiplication can be implemented using dedicated DSP blocks in the FPGA. However, the location and digit capacity of the DSP blocks are fixed. For the Altera FPGA, the width of a DSP multiplier is typically $9\times 9$ or $18\times 18$. In the cases of multiplier and multiplicand with other different widths, excess units will be unavoidable. According to the data widths of signals (8 bits) and ACE coefficients (4–7 bits), the proposed ACE can be built up based on shifter and adder without wasting units. Compared with conventional ACE, the required DSP source is shown in Table 1.

We investigate the effect of optical receiver power on the ACE performance with different multiplier-simplified levels controlled by M in the case of 10.8 km transmission. The result is compared with the performance of conventional ACE. As shown in Fig. 7, with $\mathrm{M}=7$, the performance is almost the same as the conventional ACE. By decreasing M to 6, the performance penalty of the proposed ACE is about 0.5 dB at the HD-FEC threshold of $3.8\times {10}^{-3}$. By further decreasing M to 5, the performance penalty increases to 1 dB. As the received power increases, the performance penalty becomes more obvious. This is mainly because the ACE calculation noise becomes the dominant limiting factor as the received SNR improves. When M is further reduced to 4, this impact becomes more apparent.

A multiplier-simplified ACE is proposed and experimentally demonstrated. The data processing is based on a hardware-efficient logic unit such as a shifter and an adder rather than the conventional multiplier. Trading off between the performance and power consumption, the simplification penalty can be adjusted within a selectable range. In the short-reach offline experiment, the performances of 64 Gbaud PDM-QPSK, PDM-16QAM, and PDM-64QAM are verified. The most appropriate precision of proposed ACE for different formats can be obtained from the experimental result. Typically, in 10.8 km SSMF transmission, the 64 Gbaud PDM-16QAM performance penalty can be limited to less than 0.2 dB by the proposed ACE, compared with the conventional method. Furthermore, the feasibility is confirmed by a real-time experiment. According to the transmission distance and modulation format, the proposed ACE can be built up based on a shifter and an adder without wasting logic units. Based on our 10 Gb/s PDM-QPSK real-time coherent transceiver, the proposed ACE is built up in the FPGA, and the performance is verified in 10.8 km transmission experiment. Using a reasonable number of logical units, the performance of the proposed scheme is shown to be close to that of the conventional method. Due to the large number of multiplication operations in different CV or RV FIR algorithms, it is possible to perform further simplification based on different structure-simplified ACEs in the future. In addition, the ADC sampling accuracy may be reduced as the simplification of ACE calculation accuracy.