Based on the H.265/HEVC video coding standard, a hardware pipeline structure is implemented in this study in the regular mode of a binary arithmetic encoder in CABAC coding. Based on the characteristics of the algorithm, the hardware architecture of the coding engine is designed and optimized. The probability state data are stored in a SRAM, and the probability estimation updating operation is optimized using a lookup table. The coding data are packaged to simplify the calculation obtained by the update of the probability estimation to optimize the coding speed of the video data stream. Binary arithmetic coding uses a multistage pipeline structure to support four-way parallel encoding. Simulation results show that the hardware of the CABAC binary arithmetic coder can complete the encoding of four bins per clock cycle, which satisfies the higher frame rate of 1080p video real-time encoding requirements.