Fig. 1. The structure and property of electrolyte gated NdNiO₃ transistor. (a) The crystal structure of NdNiO₃ film grown on LaAlO₃ substrate. (b) The R–T measurements for different thickness NdNiO₃ films on LaAlO₃ substrates. (c) Schematic diagram of the electrolyte-gated transistor. (d) The transfer curve. The source–drain current I_D and the gate current I_G are shown as a function of the gate voltage. Arrows indicate the gate bias sweeping direction.

Fig. 2. The dependence of the channel current on the gate spikes. (a) The same spike time (0.4 s) with different spike voltages. (b) The source–drain current I_D of (a) intercepted from 40 s is shown as a function of gate voltage. (c) The same spike voltage (+1.4 V) with different spike time. (d) The source–drain current I_D of (c) intercepted from 40 s is shown as a function of spike time. Here, the V_D was 5 mV.

Fig. 3. The conductance modulation of NdNiO₃ transistor. (a) The channel conductance changes with pulse groups. Firstly, the positive gate voltage +1.8 V with pulse width 200 ms was applied, and the pulse number is 5, 10, 15, 20, respectively. Then, the negative gate voltage −1.6 V sequence was applied, and the pulse number is 20, 15, 10, 5, respectively. All the pulse groups were spaced about 180 s. (b) Repeatability of long-term synaptic potentiation and depression.

Fig. 4. STDP characteristics of NdNiO₃ transistor device. The applied pre- and post-spikes for the (a) asymmetric and (b) symmetric STDP functions. (c) Asymmetric and (d) symmetric STDP implemented in the NdNiO₃ electrolyte-gated synaptic transistors.