A Layout Algorithm for Dynamically Reconfigurable FPGA

ZHANG Han; WU Yan-song; ZHAO Sen; MENG Cheng-dong

doi:10.3969/j.issn.1671-637x.2014.04.018

[1] PENG X M, PANG J M, GUO H R.Survey of dynamic reconfiguration technology［J］.Computer Engineering and Design, 2012, 33(12):4514-4519.

[2] CARDOSO J M P, DINIZ P C, WEINHARDT M.Compiling for reconfigurable computing:A survey［J］.ACM Computing Surveys, 2010, 42(4):13.1-13.65, doi:10.1145/1749603.1749.

[3] CHEN W, WANG Y, WANG X, et al.A new placement approach to minimizing FPGA reconfiguration data［C］//IEEE International Conference on Embedded Software and Systems, 2008:169-174.

[4] TAN H, DEMARA R F.A physical resource management approach to minimizing FPGA partial reconfiguration overhead［C］//IEEE International Conference on Reconfigurable Computing and FPGA's, 2006:1-5.

[5] ZHAO L, WANG Z, YANG L.Reliability-aware placement and fault tolerant reconfiguration in FPGAs［C］//IEEE 14th International Conference on Communication Techno-logy, 2012:541-545.

[6] LOTFIFAR F, SHAHHOSEINI H S, KHANZADI H.Dependency aware placement in reconfigurable computing systems［C］//The Second IEEE International Conference on Intelligent Systems, Modelling and Simulation, 2011:272-276.

[7] BETZ V, ROSE J, MARQUARDT A.Architecture and CAD for deep-submicron FPGAs［M］.Kluwer Academic Publishers, 1999.

[8] GAO H X.Study on design techniques of SRAM-based field programmable gate arrgy［D］.Xi'an: XiDian University, 2005.

[9] BETZ V, ROSE J.VPR:A new packing, placement and routing tool for FPGA research［C］// Field-Programmable Logic and Applications, Springer Berlin Heidelberg, 1997:213-222.

[10] SANJABI M, JAHANIAN A, AMANOLLAHI S, et al.ParSA:Parallel simulated annealing placement algorithm for multi-core systems［C］//The 16th IEEE CSI International Symposium on Computer Architecture and Digi-tal Systems, 2012:19-24.

[11] WU G M, LIN J M, CHANG Y W.Performance-driven placemen for dynamically reconfigurable FPGAs［J］.ACM Transactions on Design Automation of Electronic Systems, 2002, 7(4):628-642.

[12] BAZARGAN K, KASTNER R, SARRAFZADEH M.3-D floorplanning:Simulated annealing and greedy placement methods for reconfigurable computing systems［C］//IEEE International Workshop on Rapid System Prototyping, 1999:38-43.