Due to their flexibility in dynamic structural adjustment, Static Random Access Memory (SRAM) based Field Programmable Gate Arrays (FPGAs) are widely applied in industry and other fields.Aimed at the layout problem of modules on the reconfigurable functional unit, a hierarchical circuit partitioning-based timing-driven placement algorithm was proposed based on analysis to the limitation of the simulated annealing algorithm.The circuit was first divided into limited number of tiers based on principle of minimum cut, and then the layout of each tier was implemented according to top-down principle.The algorithm can also attain the minimum critical path delay.Experimental results show that:compared VPR algorithm, the proposed algorithm achieves better results in delay, wire-length and runtime.