
- Photonics Research
- Vol. 12, Issue 7, 1379 (2024)
Abstract
1. INTRODUCTION
Random numbers are widely used in cryptography [1], scientific simulation and computing [2], and many other fields. However, commercial random number generators (RNGs) currently face security problems in practical applications since they originate from the deterministic transformation and are predictable. In contrast, hardware RNGs based on physical processes, such as noise in electronic devices, nuclear fission, circuits, and radial decay [3–6], are believed to provide better random numbers, but it is unclear whether they can also be predicted since they are made of complex physical processes.
Quantum resources, which have natural uncertainties, are very suitable for RNG production, that is, quantum RNG (QRNG). Existing QRNG methods include single-photon detection, vacuum state fluctuations, and quantum phase fluctuations [7–10]. These QRNGs can be commercialized and deployed in many scenarios. The rise of integrated quantum technology provides a bright prospect for realizing miniaturized, compact, highly stable, scalable, and portable QRNGs, especially showing significant advantages in the size reduction of QRNG systems [11–14]. Recently, much progress has been made in integrating QRNGs [15–20].
However, hackers may control the quantum resources, causing severe security issues in all the current on-chip QRNG systems [21–24]. The device-independent (DI) scheme offers a drastic solution to the security issues of QRNGs [25–27], but the experimental realization conditions of the loop-free Bell test are harsh, and the bit rate is low [28–32]. Since the measurement devices are often simple and characterizable, the source-device-independent (SDI) approach perfectly balances the potential security risks of QRNGs and the intractability of DI scheme [21–23]. In the SDI scenario, the measurement device is assumed to be trusted, and the source is untrusted. Recently, many SDI-QRNG schemes have been proposed [33–40], solving the common security issues faced by sources in QRNG and making it secure regardless of whether hackers control the quantum resources.
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Integrating SDI-QRNG is the crucial step toward its application due to silicon-based photonics chips being ideal platforms for large-scale low-cost secure utilization at room temperature, which can greatly address the practical security risks faced by the current QRNG chips [12,41]. However, it is challenging to simultaneously guarantee the on-chip efficient utilization of quantum randomness and on-chip security of QRNG devices. Specifically, for the on-chip randomness of QRNG, realizing the on-chip high-speed and undistorted detection of quantum resources is one challenge, determining how much quantum entropy the generator can obtain. For the security of QRNG, bounding the amount of on-chip practical side channel information through a practical chip-level physical system is complex, which determines how much randomness remains secure. To the best of our knowledge, no SDI-QRNG chips have been reported so far due to the above difficulties in on-chip implementation.
In this paper, we propose an on-chip SDI-QRNG scheme that maintains the randomness in chip realization and provides security entropy evaluation criteria in a practical QRNG system, which is necessary because the chip cannot be disassembled and changed like the discrete scheme after implementation. Subsequently, a chip-level SDI-QRNG optical platform was implemented. The high-bit-rate randomness is acquired by a high-bandwidth distortion-free on-chip coherent detection and noise elimination. The security is guaranteed by maximizing the estimation of eavesdropping entropy due to the random fluctuation deviation of measurement base selection. The SDI-QRNG is integrated into a photonic circuit with a size of
2. ON-CHIP SDI-QRNG PROTOCOL
Our on-chip SDI-QRNG scheme is shown in Fig. 1. This scheme is based on the coherent detection of the vacuum state. To ensure the security of the random number generation according to the entropic uncertainty principle (EUP), we modulate the LO by a PM to achieve the on-chip random measurement basis switching, which was proposed and proven secure by Marangon
Figure 1.Schematic diagram of the integrated SDI-QRNG on SiPh PIC. GC, grating coupler; PM, phase modulator; Att, attenuator; MMI, multimode interference splitter; AWG, arbitrary waveform generator; PD, photodetector; DSO, digital signal oscilloscope. The input state is the vacuum state, and the laser is used for quadrature component measurement.
To maintain randomness on the QRNG chip, quantum randomness generation, distortion-free quantum detection, and noise interference elimination are required. For the QRNG system based on the vacuum state fluctuation, the Heisenberg uncertain relationship between the non-commutative physical quantities quadrature components
For the QRNG scheme based on vacuum states, homodyne detection is used. The relation between the annihilation operator and the quadrature component is
For the security of on-chip SDI-QRNG, we mainly consider how to realize the secure entropy evaluation in the practical situation. In theory, Marangon
The secure bound of quantum conditional minimum entropy of SDI-QRNG provided by Marangon
Considering the practical imperfections such as the modulation signal fluctuation of the PM, and the non-uniform change of carrier concentration, a phase modulation bias
Figure 2.Schematic diagram of the signal processing flow of the on-chip SDI-QRNG system based on vacuum state. (a) Generation structure of secure random bits. (b) Measurement basis switching control modulation voltage signal for secure entropy estimation. When a switching control signal pulse occurs for selecting the measurement basis of the check quadrature
The above scheme can solve the inevitable practical security problem caused by the on-chip devices with imperfect realistic conditions. It can help us evaluate more accurate security entropy in actual implementation. Therefore the above model is applicable for the presence of nonperfect factors in on-chip SDI-QRNG when it cannot be disassembled during actual chip implementation.
3. EXPERIMENT SETUP
From the consideration of implementing an efficient and secure SDI-QRNG chip, our SDI-QRNG chip system mainly consists of on-chip wide bandwidth detection of quantum resources and on-chip high-precision measurement basis switching with low half-wave modulation voltage.
A. Wide-Bandwidth Vacuum State Detection
To realize the high fidelity of on-chip quantum state detection in QRNG, a silicon-based germanium detector with a large bandwidth is realized to implement distortion-free detection, which means that the two adjacent sampling data will not affect each other. In the experiment, since the sampling signal is always within the detection bandwidth, the randomness distortion-free detection is realized. The setup to characterize the bandwidth of photodetector performance is shown in Fig. 3(a), where the input light source is a 1550 nm continuous optical laser. First, the changed RF signal is modulated to the wave amplitude as the light passes through an MZM (OSC-MOD-40Gb-460C). The RF signal is generated from the vector network analyzer (VNA, Anritsu MS46522B). The Ge absorption layer material is directly connected with the silicon waveguide, and the modulated light is directly coupled with the Ge absorption layer at the upper end by evanescent-field coupling. The modulated light is amplified by the erbium-doped fiber amplifier (EDFA) with adjustable gain before entering the PD on the chip. The electrical signals generated by the detector are separated into DC and AC signals by bias-tee. The AC signal demodulated by the detector is input into the VNA to complete the test of S21 parameters. As shown in Figs. 3(b) and 3(c), corresponding to the testing chip with the DC gold wire package and the bare chip without a package, the electro-optic S21 3 dB bandwidth of the Ge vertical photodetector is about 16.3 MHz and 27.7 GHz, under the reverse bias voltage of
Figure 3.(a) Experimental setup to characterize the bandwidth of the photodetector. Electro-optic S21 3 dB bandwidth of the (b) chip with DC gold wire package and (c) bare chip without package.
B. High-Precision Measurement Base Selection
To further improve the scheme efficiency, an on-chip modulator with high-precision measurement base selection should be implemented to greatly reduce the impact of system bit rate performance caused by the imperfection. To ensure practical security and obtain better system performance, the low and stable half-wave voltage
C. Integrated Optical System
Figure 4(a) shows the schematic diagram of the SDI-GRNG chip for the experiment, and Fig. 4(b) shows that PDs are implemented with a size of
Figure 4.Source-device-independent chip on SiPh PIC. (a) An overall microscopic view of the SDI-QRNG chip, including grating couplers (GCs), the phase modulator (PM), the attenuator (Att), and photodetectors (PDs). This overall microscopic view shows the schematic diagram of the SDI-GRNG chip for the experiment. The LO was a narrow line 1550 nm laser coupled to the chip by vertical GCs and then through a PM driven by an AWG. The AWG supplies secure random bits to control the PM when generating the selection signal of the measurement basis of the check quadrature
For basis switching, we set a ratio of 1/10 between the number of check measurements
Figure 5.Experimental homodyne measurement of the vacuum state on SiPh SDI-QRNG PIC. (a) The quadratures
For detection, a high-speed oscilloscope with 2.5 GHz bandwidth and 10 GS/s sampling rate is used for sampling. The electrical signal before sampling is within the oscilloscope’s operating range and therefore has a linear relationship with the quantized data. The nonlinearity of the analog-to-digital converter (ADC) may not have a significant impact on the measurement accuracy of the quadrature
4. RESULT
After basis-switching and on-chip vacuum state detection, we can obtain that the quantum conditional min-entropy of each frame is about 9.42 bits/sample in this frame according to Eq. (4). Considering the finite-size effect, the quantum conditional min-entropy under 250 kHz switching frequency is shown in Fig. 6 according to Eq. (6). To distill the secure random bits with more rigorous practical security, we choose the minimal quantum conditional min-entropy of the 50 frames under 250 kHz after considering the finite size effect as the conservative evaluation of the quantum conditional min-entropy used to generate the final secure random bits. Specifically, the highest min-conditional entropy is
Figure 6.The quantum conditional min-entropy of each sample under 250 kHz basis switching.
5. DISCUSSION
The above results show that this SDI-QRNG chip can generate quantum secure random numbers continuously. Moreover, once the high-frequency signal transmission limitation in packaging is solved, the theoretical secure random number rate can reach 248.87 Gbps under the highest practical detection bandwidth 27.7 GHz in the bare chip. Such a random number generation rate can fully meet data security encryption requirements, such as the one-time pad encryption algorithm. In addition, the miniaturized chip can also be placed in classical communication devices as a module to ensure data security.
The advantages of the work we present are as follows. (i) We have considered the practical security issues of the SDI-QRNG system for the first time, especially in the special physical environment of chip-level SDI-QRNG systems with non-detachable characteristics, and proposed a framework that can guarantee the practical security of the system through post-processing. (ii) Secondly, we have realized that the first simple and efficient secure SDI-QRNG chip optical platform, which overcomes the problem of simultaneously integrating high-precision PM and large bandwidth on-chip detection up to 27.7 GHz on a single chip with low power consumption, can meet the strict requirements of SDI-QRNG chip systems for on-chip manipulation and detection of quantum states. (iii) The implementation of this scheme is different from other existing DI schemes that require low-temperature superconducting nanowire detectors. It has a simple structure based on shot-noise limit detection, which is conducive to low-cost and large-scale implementation and deployment, paving the way for the large-scale application of quantum resources at room temperature.
The practical security guarantee of SDI-QRNG is a core challenge that must be considered to achieve large-scale secure applications of quantum resources, due to the nondetachable characteristic of SDI-QRNG chips. In addition, for the implementation of SDI-QRNG chips, it is crucial to have a dedicated on-chip PM that can adapt to the strict requirements of SDI-QRNG for high accuracy, high bandwidth, etc., as it determines the practical security of the chip SDI-QRNG. Meanwhile, the implementation of low half-wave voltage PM based on meeting the above requirements means low driving power consumption of SDI-QRNG, providing the possibility for further full integration and deployment in space science. Moreover, high on-chip detection bandwidth is also crucial as it determines the quality of randomness detection. Therefore, integrating both the PM and PDs on a single chip and meeting the stringent requirements of SDI-QRNG is urgently needed and important. We have overcome the above challenging issues and validated the feasibility of on-chip SDI-QRNG for the first time, which is fundamentally different from previous work [19,22,23,40] and advanced progress in the DI/SDI field.
In actual experiments, due to the advantages of our chip such as low-half wave voltage and stability, the maximum modulation angle deviation does not exceed 1°. The modulation angle deviation here is caused by the accuracy of the base selection when selecting the measurement base. Therefore, we mainly consider observing the actual accuracy of the base selection from the perspective of the half-wave voltage of the on-chip modulator. We have shown that the measured half-wave voltage of on-chip modulator in this experiment is 3.7 V in Appendix A, and the voltage we applied is the main source of nonperfection in the basis selection due to accuracy issues. The angle of deviation is determined by measuring the difference between the actual modulation voltage and the measured half-wave voltage. As the voltage we apply for base selection is also 3.7 V, considering other nonperfect factors such as voltage fluctuations and accuracy errors, we comprehensively calculate that it does not exceed 1°. In addition, in practical implementation, due to differences in the measurement deviation of half-wave voltage and the accuracy of the AWG, more imperfect modulation angles may be considered in practical scenarios based on the characterization of actual device performance. Moreover, recent researches reveal that the plasma dispersion effect may lead to phase deviation from expectations [43,44], which is included in our model, and
For implementation, it is worth noting that the feedback for enhancing the randomness of the check measurement is controlled through the PC connection, which will hinder the further miniaturization of the system. Therefore, the device will be integrated photoelectrically using PCB integration in the next step. In addition, the balanced homodyne of the system is realized by subtracting the detected optical current at the oscilloscope. Using a trans-impedance amplifier (TIA) circuit with a low-noise amplifier and field programmable gate array (FPGA) for data processing will realize further photoelectric integration and miniaturization. Besides, the optimization implementation of the circuit also needs to be further considered to reduce the crosstalk of check quadrature and further reduce the impact of external interference on the system. Finally, as an essential part of SDI-QRNG, the on-chip light source that generates LO also needs to be integrated into the system in a hybrid way.
The core of achieving a high bit rate is divided into two steps. One is to achieve a high on-chip random bit generation rate, which is mainly guaranteed by high on-chip bandwidth. The second step is to achieve a high post-processing rate commensurate with the high on-chip random bit production rate, which is guaranteed by the high computing performance of the peripheral supporting electronic circuits. Therefore, by using high computational performance custom application-specific integrated circuits such as an FPGA or an application specific integrated circuit (ASIC), the high real-time secure rates can be reasonably implemented [20]. It can be seen that our on-chip detection bandwidth has reached 27.7 GHz, so the main limitation of the bit rate here is the gold wire packaging. Therefore, we will further use the latest technologies such as high-frequency packaging to ensure that the packaging bandwidth also reaches GHz, optimizes post-processing technology, and uses higher performance GPUs, ultimately achieving a bit rate of Gbps.
Compared to other classical on-chip QRNGs such as QRNGs based on chaotic optical frequency combs, all these QRNGs have the same advantages of miniaturization, which gives them the potential to be deployed on a large scale. This work is based on quantum mechanisms, so it has information theory provable security. Meanwhile, we have considered the practical security of the system in practical implementation, which makes it more rigorous in combating actual deployment security risks. The random number generator based on chaotic optical combs is classic, and the theoretical security proof needs to be improved and faces practical security issues. The SDI-QRNG chip has demonstrated the high bandwidth bit rate on the chip, which is a promising way to achieve the same progressiveness as classic QRNG chips.
Since the SDI-QRNG scheme is designed to overcome the situation where the source is untrusted, it is necessary to make reasonable assumptions about the trusted probe end of the system. Throughout the entire life cycle of our SDI-QRNG chip principle verification experiment, our detectors are completely under our control and will not be eavesdropped by Eve.
6. CONCLUSION
In this work, we have verified the feasibility of the on-chip implementation of an SDI-QRNG optical platform in principle and implemented this SDI-QRNG chip with secure entropy generation of 8.97 bits/sample and a secure random number rate of 146.2 Mbps under the practical package detection bandwidth 16.3 MHz with all the extracted secure bits passing the randomness test. The theoretical secure random number rate can reach 248.87 Gbps under the highest measured detection bandwidth 27.7 GHz in the bare chip. Such a random number generation rate can fully meet data security encryption requirements, such as the one-time pad encryption algorithm. Our work is advanced progress in the SDI-QRNG area and is also valuable for the large-scale, low-cost exploitation and efficient utilization of the physical properties of quantum resources at room temperature.
APPENDIX A
In this appendix, we will introduce how the SDI-QRNG chip is implemented. Our contribution is the system-level establishment of the SDI-QRNG chip, and its implementation is fabricated by CompoundTek Pte Ltd. In addition, we have provided an analysis and performance testing of the core components such as the PM and PDs used in the on-chip implementation of this SDI-QRNG system. We have also analyzed the principles and technical requirements of each component in the SDI-QRNG chip system, enabling more specialized chips to be implemented in the future.
1.1 Physical Implementation of On-Chip Randomness Detection
To ensure the high-fidelity detection of the on-chip SDI-QRNG chip’s randomness, a large bandwidth on-chip detector is required. To realize the high fidelity of on-chip quantum state detection in QRNG, a silicon-based germanium detector with a large bandwidth is realized to improve the response rate. The epitaxy growth germanium detector has the advantages of CMOS compatibility, higher response speed, smaller size, and higher rate. Specifically, the PIN junction in the vertical direction was chosen to form an electronic field uniformly distributed in the vertical direction. Because the electronic field was evenly distributed in the absorption area, the response speed of the detector was further improved, and the structure could achieve a large detector bandwidth. Meanwhile, the incident light was coupled from the silicon waveguide layer to the germanium absorption layer through evanescent field coupling under this structure, which could be received by the germanium absorption layer in a short distance, with fast response speed and low dark current. Moreover, by optimizing the detector’s geometric shape and micron-level parameter design, the capacitance of the detector decreased, the impedance characteristics of the photoelectric detection circuit improved, and the carrier transit time was shortened, further enhancing the bandwidth of the detector.
To guarantee the responsivity of the detector, we need to overcome manufacturing defects caused by lattice mismatch between silicon and germanium. The buffer growth technology is adopted—growing a thin silicon-germanium buffer layer and then growing a thicker germanium buffer layer on top, thus limiting the manufacturing defects in a small area of the buffer layer and providing a top layer with low defects.
1.2 Physical Implementation of On-Chip Security
To ensure the theoretical and practical security of on-chip SDI-QRNG, a high-precision and low-power consumption on-chip PM is required. The proposed scheme can solve the inevitable practical security problem caused by on-chip devices with imperfect realistic conditions. To further improve the scheme efficiency, implementing an on-chip modulator with high-precision measurement base selection is necessary to greatly reduce the impact of system bit rate performance caused by the imperfection. To ensure practical security and obtain better system performance, implementing the low and stable half-wave voltage
1.3 Physical Implementation of On-Chip SDI-QRNG
The chip was fabricated with a Si-layer thickness of 220 nm and a buried oxide layer thickness of 2 μm at CompoundTek Pte Ltd, using its standard 90 nm lithography silicon on insulator (SOI) process. The waveguide propagation loss is approximately 1.2 dB/cm in the C band, and the coupling loss is about 4 dB per facet for Si waveguides. The half-wave voltage of the PM is 3.7 V. The PDs are implemented with a size of
Figure 7.Source-device-independent chip on SiPh PIC. (a) Photo of SDI-QRNG chip LAB device on a gas floating chip testing platform (packaged by wire bonding). The green PCB board inside is arranged neatly with gold wires to guide electrical signals for subsequent processing. (b) High-definition electron microscope image of photoelectric integration of the hybrid integrated package SDI-QRNG chip system. (c) Cross-sectional view of the photodetector.
Figure 8.(a) The structure of grating coupler. (b) The coupling loss of fiber to the waveguide at the C band. The grating period is 630 nm with a duty ratio of 50%, and the shallow etching depth of the grating region is 70 nm. The operating wavelength of the grating coupler is 1550 nm, and the coupling loss is about 4 dB per facet. The fiber to waveguide 1 dB bandwidth is about 29.5 nm.
Figure 9.(a) A cross-sectional view of the thermal phase shifter. (b) The test results of the extinction ratio versus the voltage of the thermal phase shifter. The thermal phase shifter used in the experiment is achieved by depositing a TiN layer. The height of the TiN heater is 120 nm, and the resistance is about 10–12 Ω/square. The phase shifting efficiency can be improved by the fabrication of the heat shield to reduce heat dissipation, with a dry etch 120 μm Si substrate. By adjusting the DC voltage applied to the re-attenuator, the amount of optical power input to the PD can be controlled on chip.
Figure 10.(a) Micrograph of a
Figure 11.(a) A cross-sectional view of the phase modulator. (b) Halfwave voltage of the phase modulator. The halfwave voltage of the PM has been measured with a triangular voltage sweep to verify the performance of the modulator. A 1 MHz triangular wave signal produced by the AWG was input into the modulator and the oscilloscope at the same time. The modulated signal is received by a photodetector with 1 GHz 3 dB bandwidth and subsequently loaded to the oscilloscope. As shown above, the blue line shows the received signal, and the red line shows the driving voltage.
Figure 12.(a) The experiment setup of the on-chip SDI-QRNG detector linearity. (b) The on-chip SDI-QRNG detector linearity experimental test result. As shown above, the light source is a 1550 nm laser, and an attenuator for adjusting optical power is connected behind it. The light is illuminated to the PD surface by the on-chip vertical coupler. The photocurrent generated by the PD is separated into DC and AC signals through the bias-tee, and the DC signal is measured by the precision measure unit (Keysight B2901A). The experimental data points are fitted with linear curves, and the calculated responsivity is about 0.8 A/W. What is marked in the red star is the input optical power value commonly used in QRNG experiments. Due to the limitation of the maximum input optical power under experimental conditions, no obvious saturation phenomenon has been observed, so it can be considered that the detector has excellent linearity in the working area.
Figure 13.(a) The quantum conditional min-entropy versus the minimum resolution of the quadrature data when the input is vacuum state;
Figure 14.Experimental data. (a) The raw data distribution of the quadrature
Figure 15.Auto-correlation of original quadrature-
Figure 16.The quantum conditional min-entropy of each sample under 100 kHz basis switching.
Figure 17.Schematic diagram of the Toeplitz-hashing extractor. The goal of the Toeplitz-hashing extractor is to extract the secure random bits from the experiment raw random bits by establishing the Toeplitz matrix.
Figure 18.
Figure 19.Proportion of the 15 kinds of statistical tests for the extracted random bits. The NIST test suites contain a total of 15 statistical tests. All the extracted random bits in our experiment pass the NIST test due to all the pass proportions exceeding 0.98 [46].
We implement a Toeplitz-hashing extractor to the QRNG presented in Ref. [
Although the on-chip detector bandwidth of the bare chip of our on-chip SDI-QRNG system shows in principle that the system can achieve 248.47 Gbps bit rate generation, the post-processing performance of the system will limit the actual real-time bit rate of the system. Therefore, future work will focus on improving the post-processing speed of the system by using greater computing power such as a GPU to improve the real-time bit rate generation rate of the system.
Notice that recently Toeplitz matrix hashing has been implemented for QKD privacy amplification with a block size exceeding
An important feature of the random number is randomness. In the field of random numbers, the two most commonly used standard randomness test suites are the DIEHARD and the NIST-STS statistical test suites. Standard NIST tests are applied here to verify the quality of
Additionally, the proportion of the 15 kinds of statistical tests for the extracted random bits is shown in Fig.
References
[1] C. E. Shannon. Communication theory of secrecy systems. Bell Syst. Tech. J., 28, 656-715(1949).
[2] N. Metropolis, S. Ulam. The Monte Carlo method. J. Am. Stat. Assoc., 44, 335-341(1949).
[3] W. Schindler, W. Killmann. Evaluation criteria for true (physical) random number generators used in cryptographic applications. Cryptographic Hardware and Embedded Systems (CHES), 431-449(2002).
[25] S. Pironio. Random numbers certified by Bell’s theorem. Nature, 464, 1021-1024(2010).
[26] R. Colbeck, R. Renner. Free randomness can be amplified. Nat. Phys., 8, 450-453(2012).
[49] B. Barak, R. Shaltiel, E. Tromer. True random number generators secure in a changing environment. Cryptographic Hardware and Embedded Systems (CHES), 166-180(2003).
[52] B. Barak, Y. Dodis, H. Krawczyk. Leftover hash lemma, revisited. Advances in Cryptology-CRYPTO, 1-20(2011).

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