The general pipeline architecture units and corresponding structures were proposed. It overcomes the problems that the hardware architectures consisting of delayers, selectors and multiplying units based on 3D DCT/IDCT(Discrete Cosine Transform and Inverse Discrete Cosine Transform) should use a lot of devices independently and their different blocks are not easy to be integrated. Firstly, based on the theory of 3D DCT, universal pipeline algorithm architectures compatible with positive and negative transformations were proposed. The delayer-group models by reusing delayers and selectors were set up to allow the models to be integrative and nested. Then, unit device-saving pipeline architectures and the corresponding whole pipeline architecture of 3D DCT were proposed. Finally, video signals with different formats and size blocks were processed by using this device-saving 3D DCT/IDCT pipeline architectures proposed. The experimental results indicate that the reduce ratio of number of delayers and selectors increases obviously as block size increasing by using our device-saving algorithm. When the block size reaches 64×64×64, the used number of delayers and selectors reduce by 54.7% and 44.5% respectively. It shows that the proposed method reduces the used number of delayers and selectors, meets the demand of the hardware requirements for reducing costs, improves the energy efficiency, and facilitates the integration of different block sizes.