Jing Yang, Jianshe Cao, Yaoyao Du, Lin Wang, Yufei Ma, Xing’er Zhang, Qiang Ye, Huizhou Ma, Shujun Wei, Junhui Yue, Yanfeng Sui. Design and implementation of digital delay and pulse generator of BEPC II linear accelerator[J]. High Power Laser and Particle Beams, 2020, 32(7): 074001
- High Power Laser and Particle Beams
- Vol. 32, Issue 7, 074001 (2020)
Fig. 1. Overall design of digital delay and pulse generator
Fig. 2. FPGA internal signal flow chart of each module
Fig. 3. Schematic diagram of edge detection module
Fig. 4. Behavior level simulation waveform of edge detection module
Fig. 5. Schematic diagram of multi-channel delay processing module
Fig. 6. Behavior level simulation waveform of multichannel delay processing module
Fig. 7. Clock module schematic diagram
Fig. 8. Behavior level simulation waveform of clock module
Fig. 9. Input/output circuit design
Fig. 10. Experimental platform of digital delay and pulse generator
Fig. 11. Digital delay and pulse generator test results
Fig. 12. Operation diagram of BEPC II linear accelerator’s BPM electronics and the delay generator
Fig. 13. Test waveforms of digital delay and pulse generator and beam signal
|
Table 1. Parameter requirements for digital delay and pulse generator
Set citation alerts for the article
Please enter your email address
© Copyright 2018-2021 | Chinese Laser Press. All Rights Reserved 沪ICP备15018463号-20