Aiming at the problem that achieving high frame rate for traditional column-level analog-to-digital converter (ADC) in the image sensor is difficult, a hybrid high-speed column-level ADC consisting of a successive approximation register (SAR) ADC and a single slope (SS) ADC was proposed, which reduced the conversion period by about 97% compared with the traditional SS ADC. Achieving correlated double sampling (CDS) of the pixel by the capacitance of the SAR ADC, and making a difference in the analog domain, the quantization time of CDS was shortened to one conversion period, which further improved the quantization speed of ADC. In order to ensure the linearity of column-level ADC, a 1bit redundancy algorithm was proposed, which could achieve differential nonlinearity of +0.13/-0.12 LSB and integral nonlinearity of +0.18/-0.93 LSB . Simulation results based on 180nm CMOS process show that the column-level ADC has a conversion period of only 1μs, a spurious-free dynamic range of 73.50dB, a signal-to-noise distortion ratio of 66.65dB, and an effective number of bits of 10.78bit at a clock of 50MHz.