The Software Defined Radio(SDR) requires that the Digital to Analog Converter(DAC) must have higher and higher sampling rate, and the bandwidth of the transmitted signal is wider and wider. The traditional method of the Digital Up Conversion(DUC) cannot meet the application requirements because of the limited clock frequency of the Field Programmable Gate Array(FPGA). An optimized design method of high speed DUC is proposed to improve interpolation filtering and digital frequency synthesis. Firstly, the mathematical model of high speed DUC is deduced and the traditional DUC structure is optimized and improved. The implementation structure of the efficient and flexible interpolation filtering, as well as the structure of the multichannel parallel digital frequency synthesis are designed. Secondly, the coefficients of interpolation filters are given as well as the computing method of phase parameters for parallel digital frequency synthesis. The hardware implementation shows that the function of the optimized method is correct , and the method is convenient for engineering application. The data rate of the output digital Intermediate Frequency(IF)signal can reach 960 MS/s. The optimized method can realize the interpolation of different multiples, and can also produce high speed Local Oscillator(LO) signals with different rates. It can meet the requirements of DUC applications which need to transmit wide band and high rate signals in SDR.